Circuit Simulation Algorithms Research Articles

Efficient algorithm for full-state quantum circuit simulation with DD compression while maintaining accuracy

Efficient algorithm for full-state quantum circuit simulation with DD compression while maintaining accuracy

Efficient Classical Simulation of Random Shallow 2D Quantum Circuits

A central question of quantum computing is determining the source of the advantage of quantum computation over classical computation. Even though simulating quantum dynamics on a classical computer is thought to require exponential overhead in the worst case, efficient simulations are known to exist in several special cases. It was widely assumed that these easy-to-simulate cases as well as any yet-undiscovered ones could be avoided by choosing a quantum circuit at random. We prove that this intuition is false by showing that certain families of constant-depth, 2D random circuits can be approximately simulated on a classical computer in time only linear in the number of qubits and gates, even though the same families are capable of universal quantum computation and are hard to exactly simulate in the worst case (under standard hardness assumptions). While our proof applies to specific random circuit families, we demonstrate numerically that typical instances of more general families of sufficiently shallow constant-depth 2D random circuits are also efficiently simulable. We propose two classical simulation algorithms. One is based on first simulating spatially local regions which are then “stitched” together via recovery maps. The other reduces the 2D simulation problem to a problem of simulating a form of 1D dynamics consisting of alternating rounds of random local unitaries and weak measurements. Similar processes have recently been the subject of an intensive research focus, which has observed that the dynamics generally undergo a phase transition from a low-entanglement (and efficient-to-simulate) regime to a high-entanglement (and inefficient-to-simulate) regime as measurement strength is varied. Via a mapping from random quantum circuits to classical statistical mechanical models, we give analytical evidence that a similar computational phase transition occurs for both of our algorithms as parameters of the circuit architecture like the local Hilbert space dimension and circuit depth are varied and, additionally, that the effective 1D dynamics corresponding to sufficiently shallow random quantum circuits falls within the efficient-to-simulate regime. Implementing the latter algorithm for the depth-3 “brickwork” architecture, for which exact simulation is hard, we find that a laptop could simulate typical instances on a 409×409 grid with a total variation distance error less than 0.01 in approximately one minute per sample, a task intractable for previously known circuit simulation algorithms. Numerical results support our analytic evidence that the algorithm is asymptotically efficient.4 MoreReceived 4 March 2021Revised 15 January 2022Accepted 14 February 2022DOI:https://doi.org/10.1103/PhysRevX.12.021021Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation, and DOI.Published by the American Physical SocietyPhysics Subject Headings (PhySH)Research AreasEntanglement productionPhase transitionsQuantum computationQuantum entanglementTechniquesComputational complexityInformation theoryIsing modelMatrix product statesTensor network methodsQuantum InformationStatistical Physics

Resilience of Quantum Random Access Memory to Generic Noise

Quantum random access memory (QRAM)—memory which stores classical data but allows queries to be performed in superposition—is required for the implementation of numerous quantum algorithms. While naive implementations of QRAM are highly susceptible to decoherence and hence not scalable, it has been argued that the bucket-brigade QRAM architecture [Giovannetti et al., Phys. Rev. Lett. 100, 160501 (2008)] is highly resilient to noise, with the infidelity of a query scaling only logarithmically with the memory size. In prior analyses, however, this favorable scaling followed directly from the use of contrived noise models, thus leaving open the question of whether experimental implementations would actually enjoy the purported scaling advantage. In this work, we study the effects of decoherence on QRAM in full generality. Our main result is a proof that this favorable infidelity scaling holds for arbitrary error channels (including, e.g., depolarizing noise and coherent errors). Our proof identifies the origin of this noise resilience as the limited entanglement among the memory’s components, and it also reveals that significant architectural simplifications can be made while preserving the noise resilience. We verify these results numerically using a novel classical algorithm for the efficient simulation of noisy QRAM circuits. Our findings indicate that QRAM can be implemented with existing hardware in realistically noisy devices, and that high-fidelity queries are possible without quantum error correction. Furthermore, we also prove that the benefits of the bucket-brigade architecture persist when quantum error correction is used, in which case the scheme offers improved hardware efficiency and resilience to logical errors.4 MoreReceived 21 December 2020Accepted 13 April 2021DOI:https://doi.org/10.1103/PRXQuantum.2.020311Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.Published by the American Physical SocietyPhysics Subject Headings (PhySH)Research AreasQuantum algorithmsQuantum computationQuantum information architectures & platformsQuantum information processingQuantum Information

Fast and Stable Time-Domain Simulation Based on Modified Numerical Inversion of the Laplace Transform

This article presents a new algorithm for time-domain circuit simulation based on numerical inversion of Laplace transform (NILT). The proposed method, labeled NILT n, shows that for the same computational cost of the conventional NILT, referred to as NILT0, the approximation error is reduced by a significant factor, permitting time-marching with much larger time steps and, consequently, saving significant computational cost per time step. Numerical experiments are presented to demonstrate the efficiency and accuracy of the proposed approach.

Thin-Film Transistor Simulations With the Voltage-In-Current Latency Insertion Method

This article presents formulations for the voltage-in-current (VinC) latency insertion method (LIM) for thin-film transistors (TFTs). LIM is a fast circuit simulation algorithm that solves circuits in a leapfrog manner, without requiring intensive matrix operations present in SPICE-based simulators. This allows LIM to have a far superior scaling with respect to the size of the circuit resulting in significant time savings on large circuit networks. The VinC LIM formulation for the TFTs written in this article has the benefit of a better stability compared to the original LIM formulation which allows the use of larger time steps. The performance of the new algorithm is demonstrated through the simulation of numerical examples of large flat-panel display (FPD) circuits. It is seen that VinC LIM greatly outperforms basic LIM and commercial SPICE-based simulators, where the presented algorithm is able to simulate circuits with more than 10 million nodes or devices in a reasonable time, which is not viable in many modern day SPICE-based simulators.

Voltage-in-Current Latency Insertion Method for Diodes and MOSFETs

This article presents the improved formulations for the latency insertion method (LIM) for diodes and MOSFETs utilizing the voltage-in-current framework. LIM is a fast circuit simulation algorithm, which computes the solutions to the voltages and currents in a circuit in a leapfrog manner, instead of a simultaneous matrix solution typically performed in the modified nodal analysis formalism. This allows LIM to have a far superior scaling with respect to the dimensions of the circuit. The formulations presented here have the advantage of not being limited by the stability condition in LIM and thus allow the simulations to be performed at larger time steps. Numerical examples are presented, which illustrate the improved performances of the developed formulations.

How many qubits are needed for quantum computational supremacy?

Quantum computational supremacy arguments, which describe a way for a quantum computer to perform a task that cannot also be done by a classical computer, typically require some sort of computational assumption related to the limitations of classical computation. One common assumption is that the polynomial hierarchy (PH) does not collapse, a stronger version of the statement thatP≠NP, which leads to the conclusion that any classical simulation of certain families of quantum circuits requires time scaling worse than any polynomial in the size of the circuits. However, the asymptotic nature of this conclusion prevents us from calculating exactly how many qubits these quantum circuits must have for their classical simulation to be intractable on modern classical supercomputers. We refine these quantum computational supremacy arguments and perform such a calculation by imposing fine-grained versions of the non-collapse conjecture. Our first two conjectures poly3-NSETH(a) and per-int-NSETH(b) take specific classical counting problems related to the number of zeros of a degree-3 polynomial innvariables overF2or the permanent of ann×ninteger-valued matrix, and assert that any non-deterministic algorithm that solves them requires2cntime steps, wherec∈{a,b}. A third conjecture poly3-ave-SBSETH(a′) asserts a similar statement about average-case algorithms living in the exponential-time version of the complexity classSBP. We analyze evidence for these conjectures and argue that they are plausible whena=1/2,b=0.999anda′=1/2.Imposing poly3-NSETH(1/2) and per-int-NSETH(0.999), and assuming that the runtime of a hypothetical quantum circuit simulation algorithm would scale linearly with the number of gates/constraints/optical elements, we conclude that Instantaneous Quantum Polynomial-Time (IQP) circuits with 208 qubits and 500 gates, Quantum Approximate Optimization Algorithm (QAOA) circuits with 420 qubits and 500 constraints and boson sampling circuits (i.e. linear optical networks) with 98 photons and 500 optical elements are large enough for the task of producing samples from their output distributions up to constant multiplicative error to be intractable on current technology. Imposing poly3-ave-SBSETH(1/2), we additionally rule out simulations with constant additive error for IQP and QAOA circuits of the same size. Without the assumption of linearly increasing simulation time, we can make analogous statements for circuits with slightly fewer qubits but requiring104to107gates.

Adaptive algorithm for quantum circuit simulation

Efficient simulation of quantum computers is essential for the development and validation of near-term quantum devices and the research on quantum algorithms. Up to date, two main approaches to simulation were in use, based on either full state or single amplitude evaluation. We propose an algorithm that efficiently interpolates between these two possibilities. Our approach elucidates the connection between quantum circuit simulation and partial evaluation of expressions in tensor algebra.

A novel model order reduction technique based on artificial intelligence

Computer aided design (CAD) plays a vital role in modern VLSI design. Electronic simulation is widely used to verify the design and test the behavior of the circuit before fabrication. One of the major research areas in CAD is circuit simulation. Circuit simulation is to use mathematical models to predict the behavior of an electronic circuit. A circuit is usually represented by a set of partial differential equations (PDEs) or ordinary differential equations (ODEs). So, the circuit simulation actually involves solving large-scale ODEs which sometimes takes several days or even weeks. Therefore, fast and accurate circuit simulation algorithms are needed to accelerate the simulation cycle. One way to speed up the simulation is to approximate the original system with an appropriately simplified system which captures the main properties of the original one. This method is called model order reduction (MOR), which reduces the complexity of the original large system and generates a reduced-order model (ROM) to represent the original one. There are many existing MOR methods, but there is no method that gives the best results for all of the systems. So, each system uses the best method according to its application. So, there is still a need for novel MOR techniques. This paper presents a novel MOR technique based on artificial intelligence.

Addressing Partitioning Issues in Parallel Circuit Simulation

With the rapidly increasing demands for high-speed and high-density electronic products, complexity and size of the associated circuits have increased significantly in the recent years. The large size of these circuits poses major challenges for simulation in terms of excessive CPU cost. To address this, a parallel circuit simulation algorithm has been recently developed that allows modern multicore processors to be exploited to realize higher parallel scalability with an increasing number of CPUs. In this paper, several methods have been proposed to improve efficiency and flexibility during the partitioning of analog circuits. The proposed methods reduce the constraints for partitioning, allowing a more efficient set of partitions to be found, which improves scalability when used in a parallel implementation.

Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms

The authors present a methodology geared towards EDA applications such as parasitic extraction, transient circuit simulation, and RF steady-state simulations.

A Rigorous Circuit Model for Simulation of Large-Scale Photonic Integrated Circuits

A rigorous circuit model for the simulation of large-scale photonic integrated circuit (PIC) is proposed and validated. Different from the conventional circuit theory, both guided and radiation fields are taken into consideration in the circuit model. A PIC of arbitrary size and complexity is partitioned into a collection of basic circuit elements interconnected via physical and virtual ports. The model parameters describing the terminal properties of the circuit elements are extracted by numerical techniques for photonic device simulation such as FDTD method. The performance of the entire PIC can be simulated by conventional circuit simulation algorithms based on the complex scattering matrix formalism. In contrast with the existing numerical simulation techniques, the circuit model and the simulation methodology are more flexible, efficient, and scalable for the analysis of large-scale PICs.

The Local Time Step Iterated Timing Analysis Algorithm for Circuit Simulation

Relaxation-based algorithms are efficient in simulating large-scale circuits. One of the Relaxation-based algorithms, ITA (Iterated Timing Analysis), has even been widely used in industry. Hence we present accelerating techniques to fasten ITA’s speed. The basic idea is to let ITA utilize local time steps of subcircuits as much as possible. Our techniques include a heuristic approach, a method based on Strength of Signal Flow, and the method combining the previous two techniques. Proposed methods are quite advantageous, which have been justified by real experiments.

Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation

This paper examines three algorithmic approaches for the frequency-domain harmonic-balance method in a coupled device and circuit simulator. These are the nonquasi-static, quasi-static, and modified Volterra series approaches. A detailed qualitative and quantitative comparison between these approaches is provided in terms of accuracy and the computational resources required

Decimal-coding chaos genetic algorithm for the envelope-based nonlinear microwave circuit simulation

The circuit envelope (CE) simulation technique is reviewed for the first time in this article. The concomitant models of linear devices applied in the CE simulation are discussed. Then, a method to...

Decimal-coding chaos genetic algorithm for the envelope-based nonlinear microwave circuit simulation

The circuit envelope (CE) simulation technique is reviewed for the first time in this article. The concomitant models of linear devices applied in the CE simulation are discussed. Then, a method to obtain the responses of the nonlinear circuits excited by multicarrier modulated signals is developed. A novel decimal-coding chaos genetic algorithm (DCGA) combined with the suitable crossover and mutation operations is firstly presented for solving the nonlinear equations encountered in the CE simulation. The chaos process is applied to find further ascendant solutions in the current genus space in order to update the current colony and avoid premature states in the whole evolution progress. Finally, some examples are studied to verify the validity of the DCGA. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006

A general hierarchical circuit modeling and simulation algorithm

This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced circuit matrix and compute the circuit characteristics in rational function forms for very large linear analog and interconnect circuits. We show that the exact symbolic expressions of a circuit can be obtained by finding the cancellation-free expressions from the same circuit with hierarchical definitions. Some theoretical results are characterized for the presence and conditions of cancellations in the symbolic expressions from the subcircuit reduction. A novel decancellation strategy based on a graph-based hierarchical decomposition process is proposed and canceling terms are removed both symbolically and numerically to obtain the order-reduced circuit models. The proposed method can be used for modeling and simulation of any passive or active linear circuit, which makes our method very attractive for modeling both analog circuits and resistance-capacitance-inductance interconnect circuits in both frequency and time domain. An example RC circuit is illustrated and experimental results with some large analog and interconnects circuits are presented to validate the proposed method. Our experimental results also show that subcircuit (multiple-node) reduction scheme in general is better than one-node reduction methods such as Y-/spl Delta/ transformation in terms of CPU time and memory usage.

Steady-state solution of loaded thermistor problems using an electrical equivalent circuit model

It may be quite difficult to find analytical solutions for some simple circuits containing a thermistor element. Iterative numerical procedures may also yield impractical or complicated operations including convergence problems. Often, it is not necessary to obtain a complete solution for the dynamic thermistor equation, but rather search for a steady-state response for a thermistor element. Here, circuit simulation algorithms such as SPICE can be helpful. In this study, an electrical equivalent circuit model for the steady-state NTC thermistor current–voltage characteristics at different ambient temperatures is proposed. The model includes a number of electrical equivalent circuit components (namely, diode, resistor and current source) for a piecewise-linear approximation to the current–voltage characteristic curve of an NTC thermistor. Once the electrical parameters of the loaded (self-heated) thermistor are computed at a given ambient temperature using this proposed model, then one may easily find its working (body) temperature. The performance of the method is demonstrated using a practical example. Advantages as well as limitations of the model are also discussed.

Hazard Algebras

We introduce algebras capable of representing, detecting, identifying, and counting static and dynamic hazard pulses that can occur in the worst case on any wire in a gate circuit. These algebras also permit us to count the worst-case number of signal changes on any wire. This is of interest to logic designers for two reasons: each signal change consumes energy, and unnecessary multiple signal changes slow down the circuit operation. We describe efficient circuit simulation algorithms based on our algebras and illustrate them by several examples. Our method generalizes Eichelberger's ternary simulation and several other algebras designed for hazard detection.

A Mixed Heuristic for Circuit Partitioning

As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. This paper describes a circuit partitioning algorithm which mixes Simulated Annealing (SA) and Tabu Search (TS) heuristics. The goal of such an algorithm is to obtain a balanced distribution of the target circuit among the processors of the multicomputer allowing a parallel CAD application for Test Pattern Generation to provide good efficiency. The results obtained indicate that the proposed algorithm outperforms both a pure Simulated Annealing and a Tabu Search. Moreover, the usefulness of the algorithm in providing a balanced workload distribution is demonstrated by the efficiency results obtained by a topological partitioning parallel test-pattern generator in which the proposed algorithm has been included. An extented algorithm that works with general graphs to compare our approach with other state of the art algorithms has been also included.