Abstract
Relaxation-based algorithms are efficient in simulating large-scale circuits. One of the Relaxation-based algorithms, ITA (Iterated Timing Analysis), has even been widely used in industry. Hence we present accelerating techniques to fasten ITA’s speed. The basic idea is to let ITA utilize local time steps of subcircuits as much as possible. Our techniques include a heuristic approach, a method based on Strength of Signal Flow, and the method combining the previous two techniques. Proposed methods are quite advantageous, which have been justified by real experiments.
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