Janarthanam Subramaniam Janarthanam Subramaniam from the National Institute of Electronics and Information Technology, India, talks to us about the work behind his paper ‘Fast median-finding word comparator array’, page 1402. I consider myself blessed to have the opportunity to work with Prof. David Ebenezer, who inspired me in the ethical values of research and provided guidance on publishing work. I began my research developing tunnelling current models for MOSFET and Carbon Nanotube Field Effect Transistors. Under the guidance of Prof. Ebenezer, I went on to develop nonlinear digital filters. We are interested in digital image processing, de-noising in particular. Impulse noise is not amenable to standard mathematics, physics, and linear system theory. Hence, the interest in median filtering, which is deceptively simple but does what linear system theory fails to do. There are a good number of publications in median filtering of digital images, however, hardware implementation has not taken off effectively. This is the motivation behind our Letter. We aspire to make median filter the standard de-noising block in the Image Signal Processing (ISP) environment. Pipelining and parallelism is a part of the Harvard Architecture, which is a standard platform for real-time digital processing. However, this architecture by itself is not sufficient for issues such as latency and other hardware resources. There is a need for continued systematic empirical search, which will provide enhanced support to pipelining and parallelism. The issue is non-availability of theoretical frame work. In our Letter we present a pipelined architecture of fast median-finding word comparator array. Effective parallel schemes for hardware implementation are the challenging part of hardware architecture development in signal processing system design. Most of the non-sorting methods are iterative but have smaller latency. Sorting methods are non-iterative but lead to higher latency. Under sorting methods, our proposed method addresses reduction in latency. We have reported an eight stage systolic array for an efficient median filtering technique which uses a 3×3 mask. The efficiency implies the reduction in the number of comparator stages, which results in reduced latency and fewer number of signal paths in the word comparator array. The method uses selective comparators for finding the median by avoiding comparators required to obtain fully sorted lists. The reduction in latency is the novelty of the proposed technique. This reduction is significant in the context of ISP, for example, in digital photography, cinematography, forensic science and electronic surveillance using technology such as drones. The reported method can be extended to signed integers of any data width. Non-sorting based methods in the literature involve arithmetic operations. Though new methods of median finding are being developed, extensions with parallelism and pipelining find very limited consideration. This makes it difficult to categorise the methods and related applications in hardware implementation. The most difficult challenge was the lack of theoretical support for predictable methods for efficiently sequencing comparator operations in time. This required laborious and time consuming empirical searching. De-noising in real-time applications such as electronic surveillance, digital videography and critical care biomedical electronics are the target areas for applications of the proposed method. I am working on hardware implementation of algorithms for de-noising of digital images and developing parallel and pipelined architectures for different state-of-the-art median finding methods. Since the National Institute of Electronics & IT is an electronic product design institute, it provides opportunities for us to develop and prototype algorithms for computer vision environments. Also, we are working on medical image processing for automated diagnostic system design and quality improvements. Newly developed nonlinear digital filters are being validated with state-of-the-art de-noising techniques on system level. I expect to see the development of reconfigurable nonlinear digital filters to support decision based filtering requirements. The development of hardware architecture for decision-based median filters and the design of circuits in VLSI in the context of ISP are the long-term goals. Support of reconfigurable hardware, low power VLSI and high processing capabilities in the near future will provide added advantages for achieving more significant results in this rare area of research.
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Apr 30, 2024
Bassam J. Mohd + 3
Open Access
