Hardware Implementation Of Algorithm Research Articles

Efficient computation of quaternary fixed polarity Reed-Muller expansions

A new fast algorithm for constructing the whole polarity coefficient matrices of fixed polarity Reed-Muller expansions over Galois Field GF(4) has been introduced. The matrices are generated in a recursive way making the algorithm computationally very effective in terms of basic field operations. The number of required additions and multiplications is advantageous when compared to the known Green's algorithms. It is also possible to generate fixed polarity quaternary Reed-Muller expansion in some chosen polarity without the necessity of going through all the steps and recursions of the full algorithm. Fast flow diagrams for implementation of the new algorithms in hardware have also been shown.

Recent advances of photogrammetry in robot vision

Robot vision systems are an essential part of modern robots, enabling the machine to measure, understand and interact with its environment. The dyanamic nature of a robot's task requires instantaneous feedback from the vision system, which can only be achieved by applying very simple vision processing functions or/and through the hardware implementation of algorithms. This paper gives some examples where digital close-range photogrammetry is used in severely time-constrained modes in robotics and target tracking. As a result, this survey will indicate that photogrammetric methodology does not play a significant role in robot vision yet. For future development two alternatives are foreseen in order to improve a robot's vision capabilities: (a) hardware implementation of more complex image analysis functions with consideration of photogrammetric methodology, or (b) design of a robot according to Brooks' “insect-level” intelligent system principle, based on the use of a great variety of different, simultaneous, but simple sensor functions.

A proposed hardware structure for automatic threshold selection in digital images

Since the advent of VLSI some attention has been given to the hardware implementation of algorithms. In the area of digital image analysis, threshold selection algorithms play an important role. In this paper a proposed structure for the realization of an iterative threshold selection algorithm is presented.

A High-Speed FDCT Processor for Real-Time Processing of NTSC Color TV Signal

A FDCT (fast discrete cosine transform) processor is designed to have throughput rates consistent with high speed, (real time) processing of standard National Television Systems Committee (NTSC) color television signal sampled at 3fsc = 10.7 MHz where fsc is the color subcarrier frequency. This is achieved by using a highly modular structure in a pipeline configuration. The development phase includes the selection of a suitable algorithm and the utilization of important features of the algorithm for hardware implementation. Since the prototype is used for research purposes, provisions are made for versatility of the control and selectabilifty of , the processing accuracy. The FDCT processor is capable of processing 4- or 8- or 16- point input segments and can also be used as a part of a larger system which processes a 32-point input segment. With minor modifications, the algorithm and the basic hardware design can be used for the fast inverse DCT (FIDCT) processor.

A general purpose, expandable processor for real-time computer graphics

A class of critical computer requirements for real-time scan T.V. computer graphics is examined in relation to commercially available CPU architectures. Finding general purpose processors not suited, a new processor is proposed which is designed around the concept of ‘instruction set partitioning.’ In this design, special hardware-implemented algorithms may be included in the machine instruction set, and these processors allowed to operate asynchronously from each other. The design is projected to generate a complete new frame of a color T.V. picture every 0.1-0.8 s depending on image complexity. Due to its inherent generality, the CPU may be similarly expanded to encompass a wide variety of other specialized, or real-time tasks with minimal additional hardware. The 32-bit parallel processor has a design cycle time of 100 ns and is in the price class of a minicomputer.

Implementation of a fast Fourier transform (FFT) for image processing applications

Different fast Fourier transform (FFT) algorithms for hardware implementation have been considered. We propose an implementation whereby two radix-N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup> passes are carried out in parallel and in which each N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup> -point transform is carried out via a serial input parallel output transform circuit. The processing rate is one clock cycle per input point for the N-point transform regardless of the value of N chosen. The circuit is being implemented with TTL logic and will be used to perform spatial frequency domain filtering on two dimensional infrared camera images in real time; real time meaning processing between frame display.

A Black-White Representation of a Gray-Scale Picture

A hardware-implemented algorithm combining dynamic thresholding and edge detection allows black-white representation of gray-scale images for computer storage. The output resembles a highly detailed sketch, with resolution and contrast superior to a halftone representation. The same algorithm can be applied to text and line drawings, so that all three types of images can be stored using the same compression algorithm.