Advanced Smart Power Technology Research Articles

Thin-Copper-Metal Interconnection Thermomigration Analysis in ESD Regime

Technological scaling poses severe constraints on the design of metal interconnections, particularly for ESD protection network routing in advanced smart-power technologies. A detailed analysis of thin-interconnection failure mechanisms under high power pulses and their related root causes is mandatory. In this paper, this analysis is illustrated using characterizations, failure analyses, and 3-D TCAD physical simulations data.

Synopsys HSIM-XA adopted by STMicroelectronics for its advanced Smart Power technology

Synopsys HSIM-XA adopted by STMicroelectronics for its advanced Smart Power technology

Optimization and Elimination of Parasitic Latchup in Advanced Smart-Power Technologies

This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart-power technology. The impact of logic ground isolation from the substrate and the presence p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> buried layers below the logic wells is quantified. Four different types of structures have been studied and it is demonstrated that certain ion-implantation layers that are inherently available in a standard deep submicron smart-power process due to medium and high-voltage requirements can be effectively utilized to optimize and improve the latchup performance of standard CMOS.