Abstract
This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart-power technology. The impact of logic ground isolation from the substrate and the presence p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> buried layers below the logic wells is quantified. Four different types of structures have been studied and it is demonstrated that certain ion-implantation layers that are inherently available in a standard deep submicron smart-power process due to medium and high-voltage requirements can be effectively utilized to optimize and improve the latchup performance of standard CMOS.
Published Version
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