Advanced Silicon Technology Research Articles

Nitrogen-Oxyanion-Doped HfO2 Resistive Random-Access Memory With Chemically Enhanced Forming

The high forming voltage of resistive random-access memory (RRAM) is one of the key bottlenecks for its integration in advanced silicon technology nodes. Here a nitrogen-oxyanion-doped (N-doped) hafnium oxide (HfO2) RRAM with overall improvement on forming voltage, on/off ratio and endurance is demonstrated. The critical electric field of N-doped RRAM for forming is 40% less than that of undoped RRAM. Therefore, a thicker resistive switching layer (RSL) can be used to obtain the same forming voltage, which benefits the on/off ratio and endurance performance. The N-doped RRAM achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> improvement in on/off ratio and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> improvement in endurance at the forming voltage of 2 V, a value applicable for integration with advanced silicon technology node. We propose the hypothesis that the nitrites ((NO2)−) in the RSL of N-doped devices promote forming through introducing extra chemical process as well as additional conductive paths. Physical characterization and first-principles calculations are further carried out to validate our hypothesis.

AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs

The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve area, performance, power, and scalability of many-core systems. However, reliability issue as a perpetual challenge in advanced silicon technology imperils it. Aging is an emerging reliability concern, which degrades the system's performance and causes timing failure eventually. Bias-Temperature-Instability (BTI) and Hot-Carrier-Injection (HCI) are the dominant aging mechanisms, which escalate in high temperature and stress (i.e., usage). In addition to the intra-layer temperature variations, 3D NoCs experience inter-layer temperature variations, which demand necessary investigations for aging as compared to 2D NoC. In this paper, we propose AROMa, an aging-aware deadlock-free adaptive routing algorithm integrated with a novel online aging monitoring system for 3D NoCs. The monitoring system in AROMa exploits Distributed-Centralized-Aging-Table (D-CAT) to obtain routers' aging rates for each layer of 3D NoCs periodically. Consequently, AROMa swaps between different k-best source-destination shortest paths periodically to avoid highly aged routers, force them in recovery phase of BTI, and accordingly balance aging in the network. We prove that AROMa is deadlock free. Our extensive experimental analysis using gem5 full system mode for PARSEC and SPLASH-2 benchmark suites concludes that AROMa outperforms state-of-the-art works while improving age imbalance by 70 percent and maximum age by 35 percent in 3D NoC with negligible overheads.

Development of Fan Out Package Platform for High Performance and RF Applications

ABSTRACT Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:Multiple advanced silicon technology nodesBroad range of package sizesSingle die, multi-die packagesDifferent package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer optionsSystem in Package (SiP) for RF applications An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors. In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.

IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices

It is a well-known fact that design productivity is failing to keep pace with the big increase in the demands of applications and advanced silicon technology, especially in the domain of portable electronics. Moreover owing to the massive complexity of modern systems-on-chip (SoC), complete in-house development is impossible, and thus globalization of the design process has established itself as an inevitable solution for faster and efficient design. In this global design supply chain, the design of mobile computing devices relies heavily on reusable Intellectual Property (IP) cores as a practical solution. However, such IP cores are becoming increasingly vulnerable to malicious activities, attacks and threats. Any form of third party intervention in the design process can raise grave security concerns about the system. Security issues in IP’s can be in the form of IP piracy/IP counterfeit or embedded malicious logic or information leakage. The first form of security countermeasure requires anti-piracy methodologies that can nullify false claims of ownership or detect unauthorized pirated designs. The second form of threat, which is often called a ‘hardware Trojan’, is the deliberate insertion of illicit hardware into the IP design by a rogue designer or vendor, also requires detection/correction strategies as a security countermeasure.

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.

Advances in WLCSP Technologies to Enable Cost-Reduction

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (&amp;lt;2.5mm), low pin counts (&amp;lt;25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts &amp;gt; 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

Semiconductor Surface Cleaning and Conditioning Challenges Beyond Planar Silicon Technology

The paper reviews the challenges semiconductor cleaning technology is facing in the light of: (i) advanced silicon technology moving in the direction of non-planar device structures such as 3D MOS gates, MEMS devices as well 1D nanowire-type structures, (ii) the need for modified cleans for semiconductors other than silicon, e.g. Ge and III-V compounds, and (iii) emerging needs to process surfaces of non-semiconductor substrates such as for instance sapphire in SOS (Silicon-On-Sapphire) material systems. It is concluded that in several areas significant modifications of the established cleaning technology are needed to meet emerging challenges.

Semiconductor cleaning technology for next generation material systems

This paper gives a brief overview of the challenges wafer cleaning technology is facing in the light of advanced silicon technology moving in the direction of non-planar device structures and the need for modified cleans for semiconductors other than silicon. In the former case, the key issue is related to cleaning and conditioning of vertical surfaces in next generation CMOS gate structure as well as deep 3D geometries in MEMS devices. In the latter, an accelerated pace at which semiconductors other than silicon are being introduced into the mainstream manufacturing calls for the development of material specific wafer cleaning technologies. Examples of the problems related to each challenge are considered.

Low frequency noise in biaxially strained silicon n-MOSFETs with ultrathin gate oxides

In this paper, a detailed investigation of the low frequency noise in biaxially strained-Si technology has been conducted. The noise behavior is described and compared with the results obtained on ultrathin oxide MOSFETs in an advanced silicon technology. The drain current noise measurements are interpreted by carrier number fluctuation noise models. The extracted oxide trap density is more important for the studied strained-Si devices. Finally, the important excess noise observed in the longest geometries is attributed to the gate-leakage current noise contribution.

Electronic Structure of Si1−xIVx/SiSuperlattices on Si (001)

We have preformed systematical ab initio studies of the structural andelectronic properties of short-period Si1−xIVx/Si(x = 0.125, 0.25, 0.5, IV=Ge, Sn) superlattices (SLs) grown alongthe [001] direction on bulk Si. The present calculations reveal that theSi0.875Ge0.125/Si, Si0.75Ge0.25/Si andSi0.875Sn0.125/Si are the Γ-point direct bandgapsemiconductors. The technological importance lies in the expectationthat the direct gap Si1−xIVx/Si SLs may be used ascomponents in integrated optoelectronic devices, in conjunction withthe already well-established and highly advanced silicon technology.

SOFT ERRORS IN COMMERCIAL INTEGRATED CIRCUITS

The once-ephemeral soft error has recently caused considerable concern for manufacturers of advanced silicon technology as this phenomenon now has the potential for inducing the highest failure rate of all other reliability mechanisms combined. We briefly review the three radiation mechanisms responsible for causing soft errors in commercial electronics and the basic physical mechanism by which ionizing radiation can produce a soft error. We then focus on the soft error sensitivity trends in commercial DRAM, SRAM, and peripheral logic devices as a function of technology scaling and discuss some of the solutions used for mitigating the impact of soft errors in high reliability systems.

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Test structures consisting of shallow trench isolation (STI) structures are fabricated using advanced silicon (Si) technology. Different process parameters and geometrical features are implemented to investigate the residual mechanical stress in the structures. A technology computer aided design homemade tool, IMPACT, is upgraded and optimized to yield strain fields in deep submicron complementary metal–oxide–semiconductor devices. Residual strain in the silicon substrate is measured with micro-Raman spectroscopy (μ-RS) and/or convergent beam electron diffraction (CBED) for large (25 μm) and medium size (2 μm), while only CBED is used for deep submicron STI (0.22 μm). We propose a methodology combining CBED and technology computer aided design (TCAD) with μ-RS to assess the accuracy of the CBED measurements and TCAD calculations on the widest structures. The method is extended to measure (by CBED) and calculate (by TCAD) the strain tensor in the smallest structures, out of the reach of the μ-RS technique. The capability of determining, by both measurement and calculation, the strain field distribution in the active regions of deep submicron devices is demonstrated. In particular, it is found that for these structures an elastoplastic model for Si relaxation must be assumed.

Impact of Single-Event Upsets in Deep-Submicron Silicon Technology

AbstractThe once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

An organic functional group introduced to Si(1 1 1) via siliconcarbon bond: a liquid-phase approach

We report a new liquid-phase route for alkylation of a Si surface. A Cl-terminated Si(1 1 1) surface was first prepared by UV-assisted chlorination of a H-terminated Si substrate in a PCl 5 solution. Alkylation was accomplished by a reaction of the surface SiCl groups with n-C 4H 9Li under reflux condition. We have found that the C 4H 9-terminated surface exhibits a respectable stability in air. This alkylation technique is not only simple but also effective to reduce carbon and oxygen contamination, as compared to previously reported liquid-phase processes. The SiC bonds thus formed expectedly serve as a bridge between a rich variety in organic chemistry and advanced silicon technology.

Will SIMD make a comeback

Will SIMD make a comeback

Focused ion beam sample preparation, transmission electron microscopy and electron energy loss spectroscopy analysis of advanced CMOS silicon technology interconnections

In this paper we present a dedicated technique using focused ion beam etching for transmission electron microscopy sample preparation of advanced CMOS interconnections. We show that the etching advantages are: very precise localisation allowing for thinning of small diameter contacts even when made of hard material such as tungsten or titanium nitride. The very low thickness obtained allows for high magnification observation and chemical analysis of the diffusion barrier at the bottom of small contacts by means of electron energy loss spectroscopy.

The Role of Grown-in Defects in Advanced Silicon Technology

The Role of Grown-in Defects in Advanced Silicon Technology

Quantum transport in semiconductor surface and interface channels

Advanced silicon technology developed in the early sixties brought us a two-dimensional electron system in silicon inversion layers adjacent to silicon dioxides in metal-oxide-semiconductor field-effect-transistors. In the early eighties the advancement of molecular-beam-epitaxy brought us another two-dimensional electron system in gallium arsenide inversion layers adjacent to gallium aluminum arsenide. Thus semiconductor surface and interface channels have provided us outstanding stages on which two-dimensional electron systems played the leading role in the progress of quantum transport where the quantum mechanical properties of the conduction electrons influence the transport processes. This article describes the progress in the understanding of the quantum transport over the last thirty years from the birth of the two-dimensional system till the present in as far as the author was concerned with.

Columnar microstructures in magnetron-sputtered refractory metal thin films of tungsten, molybdenum and W-Ti-(N)

Refractory metal thin films based on metals such as tungsten, molybdenum or titanium, having thicknesses of the order of 100 nm, are well known for their applicability in advanced silicon technology. These high melting point metals are commonly deposited by magnetron sputtering onto substrates at room temperature. In spite of the energetic particle bombardment of the growing films the surface mobility of the adatoms is rather limited. This, in combination with the occurrence of geometric shadowing, usually results in films exhibiting a columnar microstructure.In this paper we describe the experimental results as obtained with transmission electron microscopy using the cross-sectional technique. The successive deposition of material on the growing columns may be traced by the observation of multilayer structures, e.g. W/Ti composites. An important parameter which influences the microstructural details of the columnar structure is the internal stress state. The relationship between stresses and microstructure will therefore be illustrated, as well as the influence of the sputter gas pressure on both microstructure and stress state for the case of molybdenum thin films. Another interesting parameter which influences the columnar morphology is the chemical composition of the films. A comparison of the microstructure of pure tungsten and tungsten-rich films alloyed with titanium has shown that, apart from a one-phase to multiphase transition, the mutual alignments of the columns are different: the grains formed by similarly oriented columns are substantially larger in the binary W-Ti alloy films. Additional alloying with nitrogen gives rise to morphological changes: the incorporation of nitrogen forces the column boundaries to fade away and induces a change into a mixture of small crystallites.

Reliability, Properties and Microstructure of W80Ti20 Diffusion Barriers Between Al-Based Metallizations and Si.

ABSTRACTTungsten-rich W-Ti (or W-Ti-N) alloy films are known for their applicability as diffusion barriers in advanced silicon technology, especially in the case of aluminium-based metallizations. For a wide variety of deposition conditions and post-deposition anneal treatments these refractory-metal barriers show a columnar microstructure. In contact with aluminium the W-Ti films do not form absolute barriers, because of mutual diffusion resulting in compound formation. The reactivity of the W-Ti barriers with the Al99Si1 interconnect has been studied by in-situ resistance measurements in vacuum at temperatures of approximately 450 °C (for W-Ti alloy films) and 475 °C (for W-Ti-N alloy films). In this paper new results dealing with the relationship between deposition conditions, microstructure and barrier properties will be discussed. Furthermore, it will be shown that the actual distribution of the titanium atoms in the tungsten matrix has a substantial influence on the reactivity of the barrier film with the Al99Si1 interconnect.