Fabrication Of Advanced Semiconductor Devices Research Articles

AxBAxB… pulsed atomic layer deposition: Numerical growth model and experiments

Atomic layer deposition (ALD) is widely used for the fabrication of advanced semiconductor devices and related nanoscale structures. During ALD, large precursor doses (>1000 L per pulse) are often required to achieve surface saturation, of which only a small fraction is utilized in film growth while the rest is pumped from the system. Since the metal precursor constitutes a significant cost of ALD, strategies to enhance precursor utilization are essential for the scaling of ALD processes. In the precursor reaction step, precursor physisorption is restricted by steric hindrance (mA1) from ligands on the precursor molecules. On reaction, some of these ligands are removed as by-products resulting in chemisorbed species with reduced steric hindrance (mA1 → mA2, where mA2 < mA1) and some of the initially hindered surface reaction sites becoming accessible for further precursor physisorption. To utilize these additional reaction sites, we propose a generalized AxBAxB… pulsed deposition where the total precursor dose (ΦA) is introduced as multiple x (x > 1, x ∈ I) short-pulses rather than a single pulse. A numerical first-order surface reaction kinetics growth model is presented and applied to study the effect of AxBAxB… pulsed ALD on the growth per cycle (GPC). The model calculations predict higher GPC for AxBAxB… pulsing than with ABAB… deposition. In agreement with the model predictions, with AxBAxB… pulsed deposition, the GPC was found to increase by ∼46% for ZrN plasma enhanced ALD (PEALD), ∼49% for HfO2 PEALD, and ∼8% for thermal Al2O3 ALD with respect to conventional ABAB… pulsed growth.

Wet Etching Technology for Semiconductor and Solar Silicon Manufacturing: Part 1 - Fundamentals

Wet etching is an important step in the manufacturing of semiconductor and solar wafers and for the production of MEMS devices. While it has been replaced by the more precise dry etching technology in advanced semiconductor device fabrication, it still plays an important role in the manufacture of the silicon substrate itself. It is also used for providing stress relief and surface texturing of solar wafers in high volume. The fundamentals of wet etching silicon for semiconductor and solar applications will be reviewed. Different classes of etchants: isotropic and anisotropic: acid and alkaline will be summarized. Key features and attributes for these different etchants will be presented to give the rationale for the use of a particular etchant for a specific application.

Wet Etching Technology for Semiconductor and Solar Silicon Manufacturing: Part 2 - Process, Equipment and Implementation

Wet etching is an important step in the manufacturing of semiconductor and solar wafers and for the production of MEMS devices. While it has been replaced by the more precise dry etching technology in advanced semiconductor device fabrication, it still plays an important role in the manufacture of the silicon substrate itself. It is also used for providing stress relief and surface texturing of solar wafers in high volume. The technology of wet etching silicon for semiconductor and solar applications will be reviewed. Impact on this step for wafer properties and critical parameters (flatness, topology and surface roughness for semiconductor wafers, surface texture and reflectance for solar wafers) will be presented. The rationale for the use of a etching technology and etchant for specific applications in semiconductor and solar wafer manufacturing will be presented.

Nano-scale scratching in chemical–mechanical polishing

During chemical–mechanical polishing (CMP) in the fabrication of advanced semiconductor devices, undesirable nano-scale scratches are produced, especially in the presence of low- k dielectrics. In this paper, the lower- and upper-bound loads for scratching are estimated by contact mechanics models and are validated by AFM experiments. Additionally, the width and depth of scratches are related to such process parameters as: particle size, abrasive volume fraction, mechanical and geometric properties of the pad and surface coatings, and polishing pressure. The upper-limit for scratch width is found to be a function of the particle size and the hardnesses of the coatings and the pad. In Cu CMP this limit is about one-fifth of the abrasive diameter.

Silicon Nitride Molecular Layer Deposition Process Development using Dichlorosilane and Ammonia

Alternate processing of Dichlorosilane (DCS) and Ammonia (NH3) were used in a mini-batch furnace to deposit thin layers of silicon nitride (SiN). Applications for conformal, thin SiN films in advanced Semiconductor device fabrication are identified in literature and ITRS. Advances in furnace capabilities that enable SiN with Molecular Layer Deposition (MLD) properties are described. The MLD characteristics of SiN deposition as temperatures reduce below 520C are demonstrated through experimental results and theoretically supported by interpretation of models of Chemical Vapor Deposition (CVD) DCS:NH3 SiN.

SIMULATION OF RAPID THERMAL PROCESSING IN A DISTRIBUTED COMPUTING ENVIRONMENT

Rapid thermal processing (RTP) has become a key technology in the fabrication of advanced semiconductor devices. As wafers get larger and chip dimensions become smaller, the understanding of the highly coupled physics, such as radiative heat transfer, transient fluid flow, heat transfer, and chemical reactions through numerical modeling using high-performance computing, is the key to the design, optimization, and control of RTP reactors. In this study, an accurate and efficient simulation tool for RTP in a distributed computing environment is developed by implementing various new models and algorithms. Thegoverning equations for highly coupled and transient transport phenomena inRTP are solved by anunstructured finite volume method (FVM). Surface radiative heat transfer is the most dominant mode of heat transfer in RTP and it is modeled by the modified discrete transfer method (MDTM). The radiative properties on the patterned wafer are quite different from those on the bare silicon and they are predicted by the matrix method. To enhance thecomputationefficiency, anefficient parallelalgorithmis implemented in the solution procedure. Data communication among the processors is carried out by the Parallel Virtual Machine (PVM). To evaluate the present simulation tool, an actual commercial RTP reactor is investigated under various conditions. The accuracy of the present model is validated through the comparisons of wafer temperature profile between different models for steady state andtransient flow andheat transfer cases. To demonstrate the importance of the pattern effects in RTP systems, a transient case containing the patterned wafer is investigated. The temperature profile and its uniformity for the patterned wafer are found to be quite different from those for the unpatterned wafer. To examine the performance on parallel computation, the previous transient case is studied with different processor numbers. As the processor number increases, the computationtime is seen to reduce; however, the parallel performance is seen to degrade A larger solution iteration number and higher communication overhead are believed to be the major reasons for the degradation of the parallel performance. The present case studies indicate that the simulation tool developed in this study can be used to systematically investigate various effects in RTP systems because of its high accuracy and efficiency.

Quantitative study of chemical mechanical planarization process affected by bare silicon wafer front surface topography

Chemical mechanical planarization (CMP) is an enabling technology in the fabrication of advanced semiconductor devices. The surface topography of the starting bare silicon substrate before CMP can have a significant impact on the results of the CMP process, specifically on the uniformity of the oxide film final thickness. The quantitative studies of this phenomenon are just beginning. In this article, a laser based optical scanning measurement was used to determine the front surface topography of the bare silicon substrates prior to thermal oxide growth. Fast two-dimensional mapping of the surface height variation is obtained with very high spatial and height resolution. The one-dimensional cross-section profile extracted from the measurement is demonstrated to have good correlation with the stylus based profiler measurement. A thermal oxide layer was grown and then polished in a high efficiency planarization process on a group of substrates, which had different levels of surface topography variations on the starting surface. A signature match between the oxide thickness variation and the silicon substrate front surface topography was identified. The resultant correlation reveals the potential impact on CMP process window from the starting material due to the degradation of within-die and die-to-die uniformity. Consequently, the product yield could be threatened. The optical topographical measurement using this laser scanning measurement is demonstrated here to be capable of providing fast, vital and unique information critical to achieving satisfactory results in the oxide CMP process.

The Role of Thermal Radiative Properties of Semiconductor Wafers in Rapid Thermal Processing

AbstractRapid thermal processing (RTP) has become a key technology in the fabrication of advanced semiconductor devices. As RTP becomes the accepted technique for an increasingly wide range of processes in device fabrication, the understanding of the basic physics of radiation heat transfer in RTP systems is also being extended rapidly. This paper illustrates the use of optical models for prediction of the thermal radiative properties of semiconductor wafers. Such calculations can be used to address many of the key issues of interest in RTP, including questions concerning temperature measurement and process repeatability.