Abstract
During chemical–mechanical polishing (CMP) in the fabrication of advanced semiconductor devices, undesirable nano-scale scratches are produced, especially in the presence of low- k dielectrics. In this paper, the lower- and upper-bound loads for scratching are estimated by contact mechanics models and are validated by AFM experiments. Additionally, the width and depth of scratches are related to such process parameters as: particle size, abrasive volume fraction, mechanical and geometric properties of the pad and surface coatings, and polishing pressure. The upper-limit for scratch width is found to be a function of the particle size and the hardnesses of the coatings and the pad. In Cu CMP this limit is about one-fifth of the abrasive diameter.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
