Advanced Field Programmable Gate Array Research Articles

Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters

Calibration of models and data structures is recurring in a large number of cross-cutting applications from finance to engineering. Even though there are numerous and well-established specific calibration techniques for each application sector, using Neural Networks (NNs) can improve performance. For instance, Tapped Delay-Line Time-to-Digital Converters (TDL-TDCs) implemented in Field Programmable Gate Arrays (FPGAs) are increasingly being used in a variety of research applications, such in the time-resolved spectroscopy or in medical imaging mainly for their high-precision and flexibility. Specific decoding on the sampled information from the TDL, together with calibration to compensate for non-idealities, (i.e., Bubble Errors, BEs, and Process–Voltage–Temperature fluctuations, PVTs) are carried out for generating the conversion of digital codes to time units. In this fundamental process, the impact of Machine Learning (ML) usage has not yet been investigated. In this paper, focusing on advanced FPGA devices (i.e., 28-nm, 20-nm, and 16-nm), we propose an approach based on NNs running in Python on a standalone PC to identify the optimal conversion from digital codes to timestamps, comparing it with the classical fully FPGA-based solution c literature. The experimental validations are performed on Artix-7 (XC7A100TFG256-2) and Kintex UltraScale (XCKU040-FFVA1156-2-E) in 28-nm and 20-nm technology nodes, achieving precision of 12.9 ps r.m.s. and 4.85 ps r.m.s., respectively. These results are in line with the state-of-the-art, demonstrating that in 28-nm technology, the bubble compression algorithm is sufficient to achieve high-precision, while reordering mechanism is crucial to compensate for BEs within the 16/20-nm technology node.

Accelerating electrostatic particle-in-cell simulation: A novel FPGA-based approach for efficient plasma investigations.

Particle-in-cell (PIC) simulation serves as a widely employed method for investigating plasma, a prevalent state of matter in the universe. This simulation approach is instrumental in exploring characteristics such as particle acceleration by turbulence and fluid, as well as delving into the properties of plasma at both the kinetic scale and macroscopic processes. However, the simulation itself imposes a significant computational burden. This research proposes a novel implementation approach to address the computationally intensive phase of the electrostatic PIC simulation, specifically the Particle-to-Interpolation phase. This is achieved by utilizing a high-speed Field Programmable Gate Array (FPGA) computation platform. The suggested approach incorporates various optimization techniques and diminishes memory access latency by leveraging the flexibility and performance attributes of the Intel FPGA device. The results obtained from our study highlight the effectiveness of the proposed design, showcasing the capability to execute hundreds of functional operations in each clock cycle. This stands in contrast to the limited operations performed in a general-purpose single-core computation platform (CPU). The suggested hardware approach is also scalable and can be deployed on more advanced FPGAs with higher capabilities, resulting in a significant improvement in performance.

Custom Network Quantization Method for Lightweight CNN Acceleration on FPGAs

The low-bit quantization can effectively reduce the deep neural network storage as well as the computation costs. Existing quantization methods have yielded unsatisfactory results when being applied to lightweight networks. Additionally, following network quantization, the differences in data types between the operators can cause issues when deploying networks on Field Programmable Gate Arrays (FPGAs). Moreover, some operators cannot be accelerated heterogeneously on FPGAs, resulting in frequent switching between the Advanced RISC Machine (ARM) and FPGA environments for computation tasks. To address these problems, this paper proposes a custom network quantization approach. Firstly, an improved PArameterized Clipping Activation (PACT) method is employed during the quantization aware training to restrict the value range of neural network parameters and reduce the loss of precision arising from quantization. Secondly, the Consecutive Execution Of Convolution Operators (CEOCO) strategy is utilized to mitigate the resource consumption caused by the frequent environment switching. The proposed approach is validated on Xilinx Zynq Ultrascale+MPSoC 3EG and Virtex UltraScale+XCVU13P platforms. The MobileNetv1, MobileNetv3, PPLCNet, and PPLCNetv2 networks were utilized as testbeds for the validation. Moreover, experimental results are on the miniImageNet, CIFAR-10, and OxFord 102 Flowers public datasets. In comparison to the original model, the proposed optimization methods result in an average decrease of 1.2% in accuracy. Compared to conventional quantization method, the accuracy remains almost unchanged, while the frames per second (FPS) on FPGAs improves by an average of 2.1 times.

Method of creation of FPGA based implementation of artificial intelligence as a service

The subject of study in this article is the technologies of Field Programmable Gate Array (FPGA), methods, and tools for prototyping of hardware accelerators of Artificial Intelligence (AI) and providing it as a service. The goal is to reduce the efforts of creation and modification of FPGA implementation of Artificial Intelligent projects and provide such solutions as a service. Task: to analyze the possibilities of heterogeneous computing for the implementation of AI projects; analyze advanced FPGA technologies and accelerator cards that allow the organization of a service; analyze the languages, frameworks, and integrated environments for the creation of Artificial Intelligence projects for FPGA implementation; propose a technique for modifiable FPGA project prototyping to ensure a long period of compatibility with integrated environments and target devices; propose a technique for the prototyping of FPGA services with high performance to improve the efficiency of FPGA based AI projects; propose a sequence of optimization of neural networks for FPGA implementation; and provide an example of the practical implementation of the research results. According to the tasks, the following results were obtained. Analysis of the biggest companies and vendors of FPGA technology is performed. Existing heterogeneous technologies and potential non-electronic mediums for AI computations are discussed. FPGA accelerator cards with a large amount of High Bandwidth Memory (HBM) on the same chip package for implementation of AI projects are analyzed and compared. Languages, frameworks, and technologies as well as the capabilities of libraries and integrated environments for prototyping of FPGA projects for the AI applications are analyzed in detail. The sequence of prototyping of FPGA projects that are stable to changes in the environment is proposed. The sequence of prototyping of highly efficient pipelined projects for data processing is proposed. The steps of optimization of neural networks for FPGA implementation of AI applications are provided. An example of practical use of the results of research, including the use of sequences is provided. Conclusions. One of the main contributions of this research is the proposed method of creation of FPGA based implementation of AI projects in the form of services. Proposed sequence of neural network optimization for FPGA allows the reduction of the complexity of the initial program model by more than five times for hardware implementation depending on the required accuracy. The described solutions allow the construction of completely scalable and modifiable FPGA implementations of AI projects to provide it as a service.

Speedy light focusing through scattering media by a cooperatively FPGA-parameterized genetic algorithm.

We developed an accelerated Genetic Algorithm (GA) system based on the cooperation of a field-programmable gate array (FPGA) and the optimized parameters that enables fast light focusing through scattering media. Starting at the searching space, which influences the convergence of the optimization algorithms, we manipulated the mutation rate that defines the number of mutated pixels on the spatial light modulator to accelerate the GA process. We found that the enhanced decay ratio of the mutation rate leads to a much faster convergence of the GA. A convergence-efficiency function was defined to gauge the tradeoff between the processing time and the enhancement of the focal spot. This function allowed us to adopt the shorter iteration number of the GA that still achieves applicable light focusing. Furthermore, the accelerated GA configuration was programmed in FPGA to boost processing speed at the hardware level. It shows the ability to focus light through scattering media within a few seconds, 150 times faster than the PC-based GA. The processing cycle could be further promoted to a millisecond-level with the advanced FPGA processor chips. This study makes the evolution-based optimization approach adaptable in dynamic scattering media, showing the capability to tackle wavefront shaping in biological material.

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness

As interconnects dominate circuit performance in modern field programmable gate arrays (FPGAs), placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints and, thus, may lead to illegal routing solutions. In this article, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves a 5.1% improvement in worst slack and produce placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.

Depth Evaluation for Metal Surface Defects by Eddy Current Testing Using Deep Residual Convolutional Neural Networks

Eddy current testing (ECT) is an effective technique for evaluating depth of metal surface defects. However, in practice, evaluation primarily relies on the experience of an operator and is often carried out by manual inspection. In this article, we address the challenges of automatic depth evaluation of metal surface defects by virtual of state-of-the-art deep learning (DL) techniques. The main contributions are threefold. First, a highly integrated portable ECT device is developed, taking the advantage of an advanced field-programmable gate array (Zynq-7020 system on chip) and provides fast data acquisition and in-phase/quadrature demodulation. Second, a dataset, termed metal defects of different depths by ECT (MDDECT), is constructed using the ECT device by human operators and made openly available. It contains 48000 scans from 18 defects of different depths and liftoffs. Third, the depth evaluation problem is formulated as a time series classification problem, and various state-of-the-art 1-D residual convolutional neural networks are trained and evaluated on the MDDECT dataset. A 38-layer 1-D ResNeXt achieves an accuracy of 93.58% in discriminating the surface defects in a stainless steel sheet with depths from 0.3 to 2.0 mm in the resolution of 0.1 mm. In addition, the results show that the trained ResNeXt1D-38 model is immune to liftoff signals.

Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor

PurposeSynthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor.Design/methodology/approachA chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library.FindingsThe heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization.Originality/valueVery few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.

High-Speed Post-Processing in Continuous-Variable Quantum Key Distribution Based on FPGA Implementation

In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.

Design for the system of high‐speed data transmission and data pre‐processing for synthetic aperture radar imaging based on the system‐on‐a‐programmable‐chip

For the chirp scaling algorithm of synthetic aperture radar imaging, an efficient transmission of a large volume of data is indispensable. Prior to imaging, there is a requirement for appropriate pre-processing of the echo signal by digital down conversion (DDC). The DDC module has to remove the carrier, having an appropriate filtering processing and down-sampling processing. No matter what imaging mode is chosen, such as the stripmap mode, spotlight mode, and sliding spotlight, the needs of the whole imaging system are matched by setting a series of configurations about this pre-processing module and this transmission module. The system-on-a-programmable-chip constituted by the Advanced RISC Machine and field programmable gate array (FPGA) is the perfect experimental platform to test the performance of this system. Some of the algorithms, which are more feasible for this specific project for pre-processing in Maltab, were transplanted to FPGA using the VHSIC Hardware Description Language for functional verification. Finally, the processing results in Matlab were compared with this system to find the difference. At the same time, the time that elapsed from the 2 GB original data entering the system to the time the processed results were completely returned to the PC was also counted.

Chaos-Based Physical Unclonable Functions

The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

Abstract We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

Review of advanced FPGA architectures and technologies

Field Programmable Gate Array (FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.

SU-E-T-107: Development of a GPU-Based Dose Delivery System for Adaptive Pencil Beam Scanning

Purpose: A description of a GPU-based dose delivery system (G-DDS) to integrate a fast forward planning implementing in real-time the prescribed sequence of pencil beams. The system, which is under development, is designed to evaluate the dose distribution deviations due to range variations and interplay effects affecting mobile tumors treatments. Methods: The Dose Delivery System (DDS) in use at the Italian Centro Nazionale di Adroterapia Oncologica (CNAO), is the starting point for the presented system. A fast and partial forward planning (FP) tool has been developed to evaluate in few seconds the delivered dose distributions using the DDS data (on-line measurements of spot properties, i.e. number of particles and positions). The computation is performed during the intervals between synchrotron spills and, made available at the end of each spill. In the interval between two spills, the G-DDS will evaluate the delivered dose distributions taking into account the real-time target positions measured by a tracking system. The sequence of prescribed pencil beams for the following spill will be adapted taking into account the variations with respect to the original plan due to the target motion. In order to speed up the computation required to modify pencil beams distribution (up to 400more » times has been reached), the Graphics Processing Units (GPUs) and advanced Field Programmable Gate Arrays (FPGAs) are used. Results: An existing offline forward planning is going to be optimized for the CUDA architecture: the gain in time will be presented. The preliminary performances of the developed GPU-based FP algorithms will be shown. Conclusion: A prototype of a GPU-based dose delivery system is under development and will be presented. The system workflow will be illustrated together with the approach adopted to integrate the three main systems, i.e. CNAO dose delivery system, fast forward planning, and tumor tracking system.« less

Field-Programmable Gate Array Design of Implementing Simplex Growing Algorithm for Hyperspectral Endmember Extraction

N-finder algorithm (N-FINDR) has been widely used for endmember extraction in hyperspectral imagery. Due to its high computational complexity, developing fast computing N-FINDR has received considerable interest, specifically to take advantage of field-programmable gate array (FPGA) architecture in hardware implementation to realize N-FINDR. However, there are two severe drawbacks arising in the nature of N-FINDR design, the number of endmembers, p, which must be fixed once its value is determined in FPGA design and inconsistency in final extracted endmembers caused by different selections of initial endmembers. This paper investigates a progressive version of N-FINDR, previously known as simplex growing algorithm for its FPGA implementation which can resolve these two issues.

Discussion of the metric in characterizing the single-event effect induced by heavy ions

The single-event effect (SEE) is the most serious problem in space environment. The modern semiconductor technology is concerned with the feasibility of the linear energy transfer (LET) as metric in characterizing SEE induced by heavy ions. In this paper, we calibrate the detailed static random access memory (SRAM) cell structure model of an advanced field programmable gate array (FPGA) device using the computer-aided design tool, and calculate the heavy ion energy loss in multi-layer metal utilizing Geant4. Based on the heavy ion accelerator experiment and numerical simulation, it is proved that the metric of LET at the device surface, ignoring the top metal material in the advanced semiconductor device, would underestimate the SEE. In the SEE evaluation in space radiation environment the top-layers on the semiconductor device must be taken into consideration.

High-resolution wide-band fast Fourier transform spectrometers

We describe the performance of our latest generations of sensitive wide-band high-resolution digital Fast Fourier Transform Spectrometer (FFTS). Their design, optimized for a wide range of radio astronomical applications, is presented. Developed for operation with the GREAT far infrared heterodyne spectrometer on-board SOFIA, the eXtended bandwidth FFTS (XFFTS) offers a high instantaneous bandwidth of 2.5 GHz with 88.5 kHz spectral resolution and has been in routine operation during SOFIA's Basic Science since July 2011. We discuss the advanced field programmable gate array (FPGA) signal processing pipeline, with an optimized multi-tap polyphase filter bank algorithm that provides a nearly loss-less time-to-frequency data conversion with significantly reduced frequency scallop and fast sidelobe fall-off. Our digital spectrometers have been proven to be extremely reliable and robust, even under the harsh environmental conditions of an airborne observatory, with Allan-variance stability times of several 1000 seconds. An enhancement of the present 2.5 GHz XFFTS will duplicate the number of spectral channels (64k), offering spectroscopy with even better resolution during Cycle 1 observations.

Digital Hardware Emulation of Universal Machine and Universal Line Models for Real-Time Electromagnetic Transient Simulation

Real-time electromagnetic transient simulation plays an important role in the planning, design, and operation of power systems. Inclusion of accurate and complicated models, such as the universal machine (UM) model and the universal line model (ULM), requires significant computational resources. This paper proposes a digital hardware emulation of the UM and the ULM for real-time electromagnetic transient simulation. It features accurate floating-point data representation, paralleled implementation, and fully pipelined arithmetic processing. The hardware is based on advanced field-programmable gate array (FPGA) using VHDL. A power system transient case study is simulated in real time to validate the design. On a 130-MHz input clock frequency to the FPGA, the achieved execution times for UM and ULM models are 2.5 μs and 1.42 μs, respectively. The captured real-time oscilloscope results demonstrate high accuracy of the emulator in comparison to the offline simulation of the original system in the EMTP-RV software.

Field programmable gate array based hardware implementation of a gradient filter for edge detection in colour images with subpixel precision

Within the field of industrial image processing the use of colour cameras becomes ever more common. Increasingly the established black and white cameras are replaced by economical single-chip colour cameras with Bayer pattern. The use of the additional colour information is particularly important for recognition or inspection. Become interesting however also for the geometric metrology, if measuring tasks can be solved more robust or more exactly. However only few suitable algorithms are available, in order to detect edges with the necessary precision. All attempts require however additional computation expenditure. On the basis of a new filter for edge detection in colour images with subpixel precision, the implementation on a pre-processing hardware platform is presented. Hardware implemented filters offer the advantage that they can be used easily with existing measuring software, since after the filtering a single channel image is present, which unites the information of all colour channels. Advanced field programmable gate arrays represent an ideal platform for the parallel processing of multiple channels. The effective implementation presupposes however a high programming expenditure. On the example of the colour filter implementation, arising problems are analyzed and the chosen solution method is presented.

Hardware accelerated FPGA placement

A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic blocks, more efficient and scalable FPGA placement algorithms are needed. This paper investigates the feasibility of using hardware acceleration, in the form of FPGAs, to improve the performance of placement algorithms. An iterative algorithm is presented which exploits the fine-grain parallelism in routing individual nets. Overall, our results show that speedups of 3–4 times can be obtained, without sacrificing solution quality.