Abstract
The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.
Highlights
Modern cryptography is facing progressively more attacks directed not on cryptographic algorithms, but on their implementations—even the secured ones [1]
One can see that the phase detector (PD) bit-string generated in multiple realizations can be divided into two regions, the first, in which each m-th element is independent from the realization, and the second, where the m-th bit-string element depends on the realization number
We have chosen for tests two quite faraway models of devices: 0.18 μm Complex Programmable Logic Devices (CPLDs) and 28 nm Field-Programmable Gate Arrays (FPGAs)
Summary
Modern cryptography is facing progressively more attacks directed not on cryptographic algorithms, but on their implementations—even the secured ones [1]. There are various ways of using ring oscillators for the sake of PUFs (containing an odd number of inverters); a ring consisting of an even number of inverters can stabilize in only one of two states when powered up or, more generally, when it is initiated from an unstable state Such an architecture is called bistable ring PUF (BR-PUF) [33,34,35]; in this particular application, the inverters were replaced with more suitable cells that provide an easy cell reset (by the use of NOR gates or a dedicated architecture) as well as the ability to chose one of two gates (for the sake of PUF challenges). It turns out that chaotic systems described with simple linear one dimensional formulas can produce very complex circuit behavior [44] In such systems, the “unpredictability” results from the sensitivity to an initial condition, which affects the circuit’s state in time. The proposed circuit recursively amplifies instance differences of their electronic devices over a time
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