Advanced Digital Design Research Articles

Digital Design Tools and the Temporality of Design

Designing semiconductor chips is a complex, digitally mediated process. While already using fully digitalized tools with various affordances, chip designers continue to augment their cognitive efforts by using advanced computational tools in order to deal with growing complexity of their design tasks. The introduction of such advanced computing capabilities such as simulation introduces causal ambiguity in the process, which reconfigures the designer-tool relationship, altering the temporal rhythms of work. Through a qualitative, multi-project case study at one of the world’s largest semiconductor manufacturers, we show that different types of affordances lead to different constructions of the temporal modes of designing. We found that existing digital design tools afford a uni-threaded temporal mode of designing by a sequential ordering of human and tool actions; advanced digital design tools affords a multi-threaded temporal mode of designing by braiding together of multiple threads of human and tool ac...

Project-Oriented Approach to Low-Power Topics in Advanced Digital Design Course

We consider a problem of low-power synthesis of digital systems, which are described as a Finite State Machine (FSM). In this paper, we apply FSM decomposition technique to organize the network as a collection of alternatively working components, thus greatly reducing the switching activity of the circuit (dynamic power management). To make a decision of decomposition task more tractable, corresponding CAD tools were developed at Tallinn University of Technology. Software tools are implemented using Java technology making them compatible with a wide range of operating systems and allowing a possibility for the remote access. Actually, developed system presents interconnection of CAD tools with e-learning methodology. The primary output of this work is the development of laboratory environment that provides students with extensive hands-on opportunities to enhance their knowledge and understanding of advanced concepts and principles in low-power digital design using FPGA technology and FPGA design suits. This can add a certain level of realism to the learning experience and helps to boost student’s motivation.

Advanced digital signal processing application design will be a blast with new Xilinx Virtex 6 FPGA-based XMC and PMC boards

Advanced digital signal processing application design will be a blast with new Xilinx Virtex 6 FPGA-based XMC and PMC boards

Looks count: Computing and constructing visually expressive mass customized housing

AbstractThis paper introduces new research that seeks to develop low-cost, high quality, mass customizable building assembly systems that provide visually rich design variations for housing or other small structures. The building systems are intended to be tailored for particular cultures and communities by incorporating vernacular decorative design into the assembly design. Two complementary research areas are brought together in this work: shape grammars and digital fabrication. The visual, aesthetic aspects of the research are explored through shape grammars. The physical design and manufacturing aspects are explored through advanced digital design and fabrication technologies, and in particular, build on recent work on monomaterial assemblies with interlocking components that can be fabricated with computer numerical control machines and assembled easily by hand. The long-term objective of this research is the development of formal, visual–physical grammars with rules that generate complete computer-assisted design/computer-assisted manufacturing data for fabrication of full-scale components for assembly design variations. This paper reports on the first phase of this research: pilot studies for prototype assembly systems that incorporate vernacular languages from different parts of the world. The results of these studies are very promising, and demonstrate a spectrum of strategies for embedding visual properties in structural systems. Important next steps in this research are outlined. If successful, this work will lead to new solutions for low-cost, easily manufactured housing, which is especially critical in developing countries and for postdisaster environments. These new housing solutions will not only provide shelter but also support important cultural values through the integration of familiar visual design features. Beyond the specific context of housing and building assemblies, the research has the potential to impact the design and manufacture of designed artifacts on many scales and in many domains, especially in domains where visual aesthetics need to be considered jointly with physical, structural, or material requirements, and where design customization and variation is important.

Advanced architectures for real-time Delay-Doppler Map GNSS-reflectometers: The GPS reflectometer instrument for PAU (griPAU)

In recent years Global Navigation Satellite System’s signals Reflectometry (GNSS-R) has stood as a potential powerful remote sensing technique to derive scientifically relevant geophysical parameters such as ocean altimetry, sea state or soil moisture. This has brought out the need of designing and implementing appropriate receivers in order to track and process this kind of signals in real-time to avoid the storage of huge volumes of raw data. This paper presents the architecture and performance of the Global Positioning System (GPS) Reflectometer Instrument for PAU (griPAU), a real-time high resolution Delay-Doppler Map reflectometer, operating at the GPS L1 frequency with the C/A codes. The griPAU instrument computes 24 × 32 complex points DDMs with configurable resolution (Δ f Dmin = 20 Hz, Δ τ min = 0.05 chips) and selectable coherent (minimum = 1 ms, maximum = 100 ms for correlation loss Δ ρ < 90%) and incoherent integration times (minimum of one coherent integration period and maximum not limited but typically <1 s). A high sensitivity (DDM peak relative error = 0.9% and DDM volume relative error = 0.03% @ T i = 1 s) and stability (Δ ρ/Δ t = −1 s −1) have been achieved by means of advanced digital design techniques.

Digital System Design Using Microarchitectural Modeling

Microarchitectural modeling partitions a digital system into a data part and a control part. The data part contains registers, arithmetic and logic units (ALUs), and multiplexers. The control part can be implemented as a finite state machine, programmable logic array, or microprogram. In this paper, the method of defining a digital function in a procedural description and then applying a microarchitectural modeling technique to generate a design is presented. This methodology, which is very systematic and easy to learn, has been taught to students in an Advanced Digital Design course. Students applied the method to the design of various algorithmic specifications and produced working systems in field-programmable gate arrays (FPGAs) technologies. Class surveys indicated that students very much appreciated the power of this formal method for digital design.

Guard rings: Structures, design methodology, integration, experimental results, and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology

This paper will first focus on the guard ring structures, design methodology, integration, experimental results and analysis. In this paper, the focus will be on test structure design issues, electrical characterization, and computer aided design (CAD) methodologies for advanced digital design, and mixed signal applications. The integration of “parameterized cell” guard ring structures concept into a Cadence™ based design methodology for the construction of electrostatic discharge (ESD) structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology will be discussed. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be addressed. Additionally, this independent guard ring concept opens the door for a new methodology for RF design of primitive and hierarchical implementations.

3426 FIPER : 最新デジタル設計環境と複合領域最適化の統合

3426 FIPER : 最新デジタル設計環境と複合領域最適化の統合

Developing and Distributing Component-Level VHDL Models

The development and distribution of component-level Vhsic Hardware Descriptive Language models is essential to the successful implementation of a virtual prototyping environment based on the RASSP paradigm. In this paper we will discuss component-level modeling as it pertains to the development and distribution of simulation models in support of advanced digital signal processor system design. The paper will be partitioned into two sections pertaining to the modeling of 1) complex commercial off-the-shelf (COTS) components, and 2) standard COTS components. In addition, the paper will discuss distribution mechanisms which can be leveraged in a virtual prototyping environment. The component-level modeling discussion is based on two RASSP Technology Base efforts underway at the Georgia Institute of Technology and Mississippi State University. These efforts exemplify the RASSP program goal of creating a VHDL model library of components for the design of application specific signal processors.

A multifunction protective relay for the cogeneration industry

A multifunction relay that uses advanced digital electronic design to incorporate most (or all) of the required protection functions into one package and thereby significantly reduce the expense is described. User requirements and design considerations are examined. The discrete-Fourier-transform-based digital signal processor is discussed. Interprocessor communication and the host processor are briefly considered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VHDL Motivation

The goals of the very high speed integrated circuit (or VHSIC) program are to reduce IC design time and effectively insert VHSIC technology into military systems. These goals, indicating the need for a standard means of communication to stream-line advanced digital design and documentation, motivated the development of a hardware description language. Requirements were analyzed during 1981; program organization was formulated during 1982; and the VHSIC hardware description language (or VHDL) program was launched in August, 1983. Acting as a standard design automation interface, VHDL will simplify complex digital system design. Acting as design documentation agent, it will facilitate design insertion into electronic systems. Organization of the VHDL program is detailed elsewhere.1 We will discuss elements motivating hardware description language use (VHDL in particular) and examine its impact on governmental, industrial, and academic participation in electronic research, business, and education.

An Advanced Single-Channel NAVSTAR GPS Multiplex Receiver With up to Eight Pseudochannels

The operation of a NAVSTAR GPS multiplex receiver is defined in this paper as processor-controlled time-sharing of a single channel of receiver hardware in a manner that permits continuous (in a sampled data sense) digital phase-locked loop tracking of four GPS transmitters while simultaneously reading the 50-Hz navigation message data from the same four transmitters. The operational and performance characteristics are described for a proven advanced NAVSTAR GPS digital multiplex receiver front-end design that time-shares one code generator and one carrier synthesizer in accordance with this definition. Multiplexing has been demonstrated with this advanced single-channel receiver front-end in a manner that creates up to eight pseudochannels. The receiver can also be operated at a reduced number of pseudochannels in binary multiples of 4, 2, or 1. The eight pseudochannels provide simultaneous tracking of four GPS transmitters in P-code of both the L1 and L2 signals. In addition, the space vehicle (SV) 50-Hz navigation message data are read continuously from all four GPS transmitters. The eight pseudochannels emulate a multichannel set that is virtually free of interchannel bias and interchannel phase drift error since all GPS signals of the same frequency travel the same hardware path. Sixteen observables are continuously available: four L1 code phases, four L2 code phases, four L1 carrier doppler phases, and four L2 carrier doppler phases. These measurements are captured directly as a by-product of the nearly instantaneous phase presetting and the digital synthesis of the numerically controlled code and carrier tracking loops. From these raw measurements, the usual GPS receiver pseudoranges, delta pseudoranges, and their L1/L2 differences can be derived. Quantization noise is negligible since the raw measurements are of such ultrahigh resolution (2−16 P-chip code phase and 2−16 cycle carrier doppler phase). The receiver error characteristics are described and actual tracking error plots for 16 simultaneous observables from four real GPS satellites are shown.