Developing and Distributing Component-Level VHDL Models

Abstract

The development and distribution of component-level Vhsic Hardware Descriptive Language models is essential to the successful implementation of a virtual prototyping environment based on the RASSP paradigm. In this paper we will discuss component-level modeling as it pertains to the development and distribution of simulation models in support of advanced digital signal processor system design. The paper will be partitioned into two sections pertaining to the modeling of 1) complex commercial off-the-shelf (COTS) components, and 2) standard COTS components. In addition, the paper will discuss distribution mechanisms which can be leveraged in a virtual prototyping environment. The component-level modeling discussion is based on two RASSP Technology Base efforts underway at the Georgia Institute of Technology and Mississippi State University. These efforts exemplify the RASSP program goal of creating a VHDL model library of components for the design of application specific signal processors.