Advanced Complementary Metal Oxide Semiconductor Research Articles

Advanced CMOS manufacturing of superconducting qubits on 300 mm wafers

The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1,2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.

Effects of Fe Contamination on the Reliability of Gate Oxide Integrity in Advanced CMOS Technology

Fe contamination has always been one of the most critical issues in the integrated circuit (IC) industry due to its catastrophic effect on device reliability and electrical characteristics. With complementary metal oxide semiconductor (CMOS) technology scaling down, this issue has been attracting more attention. In this paper, the impact of Fe impurity on the reliability of gate oxide integrity (GOI) in advanced CMOS technology is investigated. Intentional contamination of polysilicon gates was conducted in both boron- and phosphorus-doped devices. Failure analysis of the gate oxide was conducted with high-resolution transmission electron microscopy (HRTEM) and the energy dispersive X-ray (EDX) technique. The experimental results disclose that the properties of PMOS are much more sensitive to Fe contamination than those of NMOS. It is suggested that the reason for the above phenomena is that Fe precipitates at the PMOS gate/oxide interface but dissolves uniformly in the NMOS poly gate due to lower formation energy of the FeB pair (0.65 eV) in PMOS than that of the P4-Fe cluster (3.2 eV) in NMOS.

New structure transistors for advanced technology node CMOS ICs.

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g.in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

Dopant Engineering of Hafnia-Based Ferroelectrics for Long Data Retention and High Thermal Stability.

Hafnia-based ferroelectrics have gained much attention because they can be used in highly scaled, advanced complementary metal-oxide semiconductor (CMOS) memory devices. However, thermal stability should be considered when integrating hafnia-based ferroelectric transistors in advanced CMOS devices, as they can be exposed to high-temperature processes. This work proposed that doping of Al in hafnia-based ferroelectric material can lead to high thermal stability. A ferroelectric capacitor based on Al-doped hafnia, which can be used for one-transistor-one-capacitor applications, exhibits stable operation even after annealing at 900°C. Moreover, it demonstrates that the ferroelectric transistors based on Al-doped hafnia for one-transistor applications, such as ferroelectric NAND, retain their memory states for 10 years at 100°C. This study presents a practical method to achieve thermally stable ferroelectric memories capable of enduring high-temperature processes and operation conditions.

Significant Resistance Reduction in Modulation‐Doped Silicon Nanowires via Aluminum‐Induced Acceptor States in SiO2

Silicon nanowires (Si NWs) like structures in the form of nanosheets are the building blocks for future transistors in the most advanced complementary metal–oxide–semiconductor technologies. However, Si NWs with few nanometers in diameter suffer from severe difficulties with respect to efficient impurity doping. These difficulties can be overcome by a novel doping concept for Si NWs comparable to the modulation doping approach known from III–V semiconductors. Modulation doping means that the parent dopant atoms are spatially separated from the volume that is to be doped by embedding them into an adjacent material with a higher bandgap. Herein, Al‐doped SiO2 shells around the Si NWs are used for the experimental realization of modulation doping. In two independent experiments, a significant reduction of the electrical resistance of Si NWs by several orders of magnitude is measured, when compared to the resistance of Si NWs with undoped SiO2 shells. The results are discussed in the context of modulation doping by the surface functionalization with SiO2:Al shells.

Effect of ammonium halide salts on wet chemical nanoscale etching and polishing of InGaAs surfaces for advanced CMOS devices

Wet surface treatment of InGaAs is crucial for high-performance complementary metal-oxide semiconductor (CMOS) devices as it reduces material loss and oxide formation in the InGaAs layer. In this present study, the surface chemistries of In0.53Ga0.47As during wet chemical etching and the chemical-mechanical planarization (CMP) process in acidic (HCl/H2O2/H2O mixture) and alkaline (NH4OH/H2O2/H2O mixture) solutions were investigated. Elemental oxide formation, surface termination, and stoichiometry after the chemical etching/CMP process were investigated through X-ray photoelectron spectroscopy and atomic force microscopy. In wet chemical etching, the dissolution of the InGaAs elemental oxide was more prominent in acidic HCl mixture solutions compared to alkaline NH4OH mixture solutions. It was observed that the overall surface etching was more aggressive in acidic solution, whereas the alkaline solution provided higher surface roughness (Ra, ∼7.19 nm, scanning area of 5 μm × 5 μm) due to the lower dissolution capacity of indium oxide. The effects of the oxidizer and the slurry pH on the removal rate, Ra, and surface contamination were evaluated after the InGaAs CMP process. A high removal rate (∼110 nm/min) and considerably lower surface contamination were obtained using an alkaline slurry (pH 10). A novel InGaAs CMP slurry is developed by adding different ammonium halide salts to the alkaline slurry for improving surface roughness and removal rate. The addition of ammonium halide salts to an alkaline slurry was very effective in achieving a higher removal rate (∼175 nm/min) and smoother surface (Ra < 0.6 nm) with lower contamination during the InGaAs CMP process.

3D Integrated Laser Attach Technology on a 300-mm Monolithic CMOS Silicon Photonics Platform

Enabling cost-effective and power-efficient laser source on a silicon photonics (SiPh) platform is a major goal that has been highly sought after. In the past two decades, tremendous effort has been made to develop various on-chip integration techniques to enhance SiPh circuits with efficient light-emitting materials. Here we review our recent advancements in hybrid flip-chip integration of III-V lasers on a 300-mm monolithic SiPh platform. By leveraging advanced complementary metal oxide semiconductor (CMOS) manufacturing processes, we have demonstrated wafer-scale laser attach based on a precisely controlled cavity formed on a silicon-on-insulator (SOI) substrate. The laser integration process is aided by precise mechanical alignment features on the SiPh wafer and high-precision fiducials on the laser. Efficient laser-to-SiPh-circuit butt-coupling with optical power up to 20mW was demonstrated through wafer- and module-level characterizations. Key performance metrics including side-mode suppression ratio, mode-hopping, and relative intensity noise were characterized after laser integration. In addition, early reliability assessments were performed on laser-attached SOI wafers and Si submount assemblies to understand the long-term performance stability of the lasers on the monolithic platform. To further enhance the performance of the laser-integrated chip, we explored alternative spot-size converters that could simultaneously enable improved coupling efficiency and relaxed fabrication tolerance, thus showing great promise over traditional designs.

Fabrication technology of void embedded silicon-on-insulator substrate

Void embedded silicon-on-insulator (VESOI) substrate is a newly developed silicon-on-insulator (SOI) substrate for advanced complementary metal oxide semiconductor (CMOS) devices and integration technology. However, in the ion-cutting process for preparing the substrate, numerous hydrogen bubbles aggregate at the cut interface, which compresses the cavity structure and might cause the thin film above the cavity to be damaged and delaminated. Therefore, it is necessary to conduct in-depth research on the stress mechanism and process stability in the preparation of VESOI substrates. This study focuses on a single rectangular cavity structure and uses the fixed-supported beam theory to analyze its mechanical behavior during fabrication, and a three-dimensional model of cavity structure is constructed by using the finite element analysis tool. Through stress simulation, the failure mechanism of the cavity structure is identified, and the weak points are confirmed. The results show that the short side length (&lt;i&gt;w&lt;/i&gt;), top silicon film thickness (&lt;i&gt;t&lt;/i&gt;), and hydrogen bubble pressure are the main factors affecting the stress state of the top silicon film. When the &lt;i&gt;w&lt;/i&gt;/&lt;i&gt;t&lt;/i&gt; ratio exceeds 4–5, the silicon film will fracture owing to excessive tensile stress, and the fracture site is along the long side of the rectangular cavity. By increasing the thickness of the top silicon film slightly and adding support structures inside the cavity (to reduce &lt;i&gt;w&lt;/i&gt;), this work successfully prepares high-quality 8-inch VESOI substrates that meet the requirements for the CMOS production line. The present study is expected to provide valuable idea for the development of integrated technologies relying on VESOI substrates.

Relationship between Atomic Structure, Composition, and Dielectric Constant in Zr–SiO2 Glasses

Computational methods, or computer-aided material design (CAMD), used for the analysis and design of materials have a relatively long history. However, the applicability of CAMD has been limited by the scales of computational resources generally available in the past. The surge in computational power seen in recent years is enabling the applicability of CAMD to unprecedented levels. Here, we focus on the CAMD for materials critical for the continued advancement of the complementary metal oxide semiconductor (CMOS) semiconductor technology. In particular, we apply CAMD to the engineering of high-permittivity dielectric materials. We developed a Reax forcefield that includes Si, O, Zr, and H. We used this forcefield in a series of simulations to compute the static dielectric constant of silica glasses for low Zr concentration using a classical molecular dynamics approach. Our results are compared against experimental values. Not only does our work reveal numerical estimations on ZrO2-doped silica dielectrics, it also provides a foundation and demonstration of how CAMD can enable the engineering of materials of critical importance for advanced CMOS technology nodes.

An improved frequency compensation for three‐stageCMOSamplifier

AbstractMulti‐stage operational amplifiers are considered as basic building blocks in modern electronics since advanced Complementary metal–oxide–semiconductor (CMOS) technology limits exploiting cascode structures due to suffering from low voltage swings and the need of high gain capability. In this regard, an improved and high‐performance three‐stage CMOS amplifier is proposed in this work. The presented structure modeled mathematically and simulated via HSPICE circuit simulator with the 0.18‐μm CMOS technology. An straightforward symbolic calculation is explained to obtain linear transfer function. According to the simulation results, the proposed circuit show 149 dB as DC gain while express 7.3 MHz and 380 μW as gain‐bandwidth product and power dissipation, respectively. Such a high‐performance amplifier has great potential to realize more complex analog and mixed mode signal systems such as modulators and data convertors.

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O2 to AlN and Related Materials

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O₂ to AlN and Related Materials

Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification

The voltage amplification of a ferroelectric layer was studied for advanced complementary metal–oxide–semiconductor (CMOS) applications. To match the capacitance for negative-capacitance field-effect transistors (NC-FETs), a method of adjusting the MOS capacitance is proposed by optimizing the width (W) and height/depth (H) in two types of ferroelectric gate-stack 2D metal-oxide semiconductor capacitor (MOSCAP) structures: a fin-like structure and a trench structure. The capacitance of the semiconductor was modeled to match that of the ferroelectric films to obtain hysteresis-free operation (ΔVT = VT, for –VT,rev ~ 0) and achieve voltage amplification (AV). The optimized conditions are found to be H = 19.3 nm and 24.3 nm to achieve the criterion with AV > 50 for the fin-like and trench structure, respectively. Subsequently, the structure was extended to a three-dimensional (3D) fin-shaped field-effect transistor (FinFET) to evaluate the effects of varying geometrical parameters such as the fin spacing (FS). Tuning FS can not only enhance the on-current but also decrease the subthreshold swing in the off-current region. For the FET, the use of the optimum FS value of 30 nm helps the FinFETs achieve capacitance matching with AV > 30. The subthreshold swing of the NC-FinFET is improved by about 47% for HFinFET/WFinFET ~ 3 and Fs/HFinFET ~ 1.2 as compared with the conventional FinFET. The concept of coupling the polarized Hf-based oxide in NC-FETs that is demonstrated to be feasible herein is thus practicable using current CMOS architectures.

Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> ) was investigated in detail. Parasitic series resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sd</sub> ) noticeably decreased as V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> increased. In addition, transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), its derivative (dg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gf</sub> ), and ON-drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) in a short-channel JLT were significantly affected by the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> -modulated R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sd</sub> with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III-V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices.

Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications.

Ion-sensitive field-effect transistors (ISFETs) form a high sensitivity and scalable class of sensors, compatible with advanced complementary metal-oxide semiconductor (CMOS) processes. Despite many previous demonstrations about their merits as low-power integrated sensors, very little is known about their noise characterization when being operated in a liquid gate configuration. The noise characteristics in various regimes of their operation are important to select the most suitable conditions for signal-to-noise ratio (SNR) and power consumption. This work reports systematic DC, transient, and noise characterizations and models of a back-end of line (BEOL)-modified foundry-made ISFET used as pH sensor. The aim is to determine the sensor sensitivity and resolution to pH changes and to calibrate numerical and lumped element models, capable of supporting the interpretation of the experimental findings. The experimental sensitivity is approximately 40 mV/pH with a normalized resolution of 5 mpH per µm2, in agreement with the literature state of the art. Differences in the drain current noise spectra between the ISFET and MOSFET configurations of the same device at low currents (weak inversion) suggest that the chemical noise produced by the random binding/unbinding of the H+ ions on the sensor surface is likely the dominant noise contribution in this regime. In contrast, at high currents (strong inversion), the two configurations provide similar drain noise levels suggesting that the noise originates in the underlying FET rather than in the sensing region.

High Sensing Performance of Nanoimprinted HfO2 Sensing Membrane for Electrode-Insulator-Semiconductor pH Sensors

In this paper, HfO2 thin films as a sensing membrane deposited on nanoimprinted Si substrates by both atomic layer deposition (ALD) and sputtering methods were investigated for an electrolyte–insulator–semiconductor (EIS) pH sensor application. X-ray diffraction, X-ray photoelectron spectroscopy and atomic force microscopy were performed to examine the crystalline structures, chemical compositions and surface morphologies of the HfO2 sensing films, respectively. The structural properties of these HfO2 films were correlated to their sensing performances. Compared with the sputtering method, the unpatterned HfO2 sensing film by the ALD method showed a higher pH sensitivity of 55.06 mV pH−1, a lower drift rate of 0.31 mV h−1 and a smaller hysteresis voltage of 0.90 mV. The high pH sensitivity and good stability may be attributed to the increase in surface roughness and the reduction of a silicate layer caused by the ALD method. Additionally, the ALD-HfO2 EIS sensor deposited on the nanoimprinted Si substrate demonstrated a Nernstian pH response (61.36 mV pH−1) than that on an unpatterned Si substrate. For compatibility with advanced complementary metal–oxide–semiconductor technology, the ALD-HfO2 sensing film deposited on the nanoimprinted Si substrate is a promising candidate for pH sensing applications.

A cryogenic CMOS chip for generating control signals for multiple qubits

Scaled-up quantum computers will require control interfaces capable of the manipulation and readout of large numbers of qubits, which usually operate at millikelvin temperatures. Advanced complementary metal–oxide–semiconductor (CMOS) technology is an attractive platform for delivering such interfaces. However, this approach is generally discounted due to its high power dissipation, which can lead to the heating of fragile qubits. Here we report a CMOS-based platform that can provide multiple electrical signals for the control of qubits at 100 mK. We demonstrate a chip that is configured by digital input signals at room temperature and uses on-chip circuit cells that are based on switched capacitors to generate static and dynamic voltages for the parallel control of qubits. We use our CMOS chip to bias a quantum dot device and to switch the conductance of a quantum dot via voltage pulses generated on the chip. Based on measurements from six cells, we determine the average power dissipation for generating control pulses of 100 mV to be 18 nW per cell. We estimate that a scaled-up system containing a thousand cells could be cooled by a commercially available dilution refrigerator. A platform based on complementary metal–oxide–semiconductor (CMOS) technology operating with qubits close to 100 mK can generate static and dynamic signals for the control of many qubits.

Effect of Statistical Dopant Fluctuations on Threshold Voltage of Emerging Devices

This paper presents a comparative study on the effect of statistical dopant fluctuations on threshold voltage (Vth) of emerging and conventional metal-oxide-semiconductor (MOS) field-effect (FET) transistors (MOSFETs). In this context, three n-channel MOSFET structures representing three different complementary MOS (CMOS) technologies at the 20 nm node are considered. The structures represent a conventional device with symmetric halo or pocket regions around the n+source-drain formed by a single p-type dopant implantation; a second conventional device with symmetric p-type halo regions around the n+source-drain formed by multiple p-type dopant implantations; and an emerging epitaxial-channel device with symmetric p-type halo regions around the n+source-drain where the halo regions are formed by up-diffusion of multiple p-type buried layers from the bulk-substrate during epitaxy. For these devices, the values of Vth variance and mismatch are computed as a function of device dimensions. The results show that the multiple-halo devices, in general, offer significantly lower Vth variance and mismatch compared to the conventional single-halo devices whereas, the emerging epitaxial-channel multiple-halo MOSFETs offer the lowest Vth variability compared to the conventional devices at the same technology node. And, the value of the mismatch coefficient for the emerging technology is about 0.68 mV × μm compared to that of 1.33 and 1.07 mV × μm for the conventional single-halo and multiple-halo technologies, respectively. This study, clearly, demonstrates the benefit of the emerging epitaxial-channel buried-halo MOSFETs in significantly reducing the effect of statistical dopant fluctuations on Vth at the advanced planar CMOS technology nodes.

Simple estimation of intrinsic electrical parameters in junctionless transistors

Junctionless transistors (JLTs) are an attractive candidate for advanced complementary metal oxide semiconductor technologies, but their mode of operation is very different from that of conventional inversion-mode transistors. In this study, we explore the close relationship between the key electrical parameters of JLTs, such as doping concentration (Nd), threshold voltage (Vth), and flat-band voltage (Vfb). The separation between Vfb and Vth in JLTs increases linearly with Nd, and the rate of increase in the separation was affected by the maximum depletion depth (Dmax) at given Nd. These findings will enable researchers to estimate simply the Nd or Vfb values of not only JLTs but also JLT-like multi-layer transition metal dichalcogenide-based transistors.

State of the Art and Future Perspectives in Advanced CMOS Technology.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

A monolithic bipolar CMOS electronic–plasmonic high-speed transmitter

To address the challenge of increasing data rates, next-generation optical communication networks will require the co-integration of electronics and photonics. Heterogeneous integration of these technologies has shown promise, but will eventually become bandwidth-limited. Faster monolithic approaches will therefore be needed, but monolithic approaches using complementary metal–oxide–semiconductor (CMOS) electronics and silicon photonics are typically limited by their underlying electronic or photonic technologies. Here, we report a monolithically integrated electro-optical transmitter that can achieve symbol rates beyond 100 GBd. Our approach combines advanced bipolar CMOS with silicon plasmonics, and addresses key challenges in monolithic integration through co-design of the electronic and plasmonic layers, including thermal design, packaging and a nonlinear organic electro-optic material. To illustrate the potential of our technology, we develop two modulator concepts—an ultra-compact plasmonic modulator and a silicon-plasmonic modulator with photonic routing—both directly processed onto the bipolar CMOS electronics. The monolithic integration of electronic and plasmonic technologies can be used to create electro-optic transmitters capable of symbol rates beyond 100 GBd.