Adjacent Channel Leakage Ratio Research Articles

Design of continuous mode Doherty power amplifiers using generalized output combiner

In this paper, a continuous mode Doherty power amplifier (DPA) working over an octave bandwidth is constructed using a generalized combiner. The generalized combiner provides the PA designers with more freedoms for realizing broadband DPAs. Theoretically, the generalized combiner could expand the working bandwidth of continuous mode DPA. A continuous mode DPA working over 1.2–2.7 GHz (a relative bandwidth of 76.9%) is implemented in this contribution for demonstrating the universality of the generalized combiner. As a demonstrator circuit, the fabricated DPA achieves drain effciencies of 40–54% and 44–75% at 6 dB back-off and saturation power levels, respectively. The maximum output power of the fabricated DPA is 42.1–44.2 dBm with a saturation gain of 7.2–11.3 dB over 1.2–2.7 GHz. When the designed DPA is excited by a 20 MHz LTE signal with a peak to average power ratio of 7.04 dB, the fabricated DPA achieves adjacent channel leakage ratios (ACLRs) of −29.5 dBc and −49.5 dBc at 2.4 GHz before and after DPD technique, respectively.

A Crest Factor Reduction Scheme with Optimum Spacing Peak Cancellation for Intra-band Non-contiguous Carrier Aggregated OFDM Signals

This paper proposes a new crest factor reduction scheme to reduce instantaneous-to-average power ratio (IAR) resulting decent peak reduction, and adjacent channel leakage ratio (ACLR) reduction, though the error vector magnitude (EVM) is significantly enhanced. In the conventional peak cancellation (CPC) technique, peak regrowth occurs as a result of finite impulse response (FIR) filter windows overlapping. The peak regrowth problem in CPC technique can be compensated, though this will lead to increased computational complexity and degradation in EVM. The proposed algorithm allocates spacing to contiguous peaks to avoid FIR filter windows overlapping. Two types of overlapping are discussed, incremental and decremental. The optimum spacing can be determined from the FIR filter impulse response characteristic. Simulations are carried out with different intra-band non-contiguous carrier aggregated OFDM signals. The results of simulations show between 3 and 10% improvement in EVM performance while maintaining equivalent IAR and ACLR performance. Applying the proposed optimum spacing peak cancellation scheme compared to the conventional peak cancellation technique.

Empowering the Bandwidth of Continuous-Mode Symmetrical Doherty Amplifiers by Leveraging on Fuzzy Logic Techniques

Achieving a fractional bandwidth (FBW) of more than 60% has been a challenging problem for two-way symmetrical Doherty power amplifiers (TW-SDPAs) that are designed using a continuous-mode technique. As reported in the literature, these designed continuous-mode-based TW-SDPAs possess less than 52% FBW, which cannot satisfactorily meet the challenging, complex, and ever-evolving modulation schemes' demands. To overcome such a limitation, this article proposes a novel approach based on fuzzy logic techniques able to simplify and speed up the design of continuous-mode-based TW-SDPAs with the state-of-the-art FBW. In particular, the proposed technique uses the K -means unsupervised learning clustering algorithm and the continuous-mode technique in a modeled fuzzy logic system environment. As a result, extensive impedance solution design space is readily made available and the optimal impedances required by the carrier and peaking subamplifiers for efficiently operating at the saturation and output-power-back-off (OPBO) levels are automatically obtained. For verification, a TW-SDPA was designed and measured. According to the measured results, the TW-SDPA operates within the 1.2-2.4-GHz frequency band corresponding to 66.7% FBW. As compared with the designed continuous-mode-based TW-SDPAs reported in the literature, this article indicates over 15% increment in FBW. Moreover, 41.59%-81.1% drain efficiency (DE) at saturation, 35%-63% DE at 6-dB OPBO, 42-45-dBm output power, and 7-10.52-dB gain were successfully achieved. Adjacent channel leakage ratio (ACLR) better than -46 dBc and average DE within 46%-55% were successfully recorded after linearization.

A Fully Integrated Reconfigurable Multimode Class-F2,3 GaN Power Amplifier

In this letter, we propose a reconfigurable multimode fully integrated power amplifier (PA) in GaN technology. The PA is composed of one main transistor, biased in class-AB, and three auxiliary transistors which can be switched between class-AB and deep class-C, to improve efficiency and linearity of the PA. Furthermore, a harmonic termination network is proposed to enable the operation of the PA in class-F2,3. A proof-of-concept PA, fabricated using a 250-nm GaN-on-SiC process, provides 33.8-dBm output power and 42% peak drain efficiency (DE) at 4.8 GHz. Modulated-signal measurements using a 200-MHz 256-QAM 7.2-dB peak-to-average power ratio (PAPR) signal indicate that rms error vector magnitude (EVMrms) of < 5% (−26 dB) can be achieved with 27.7–28.5 dBm average output power, 26%–30% average DE, and −38.1 to −33.5 dBc adjacent channel leakage ratio (ACLR), in the four operation modes. It is shown that ACLR can be improved by 6 dB at lower output power levels through reconfiguring the mode of PA operation.

Efficient Digital Predistortion Using Sparse Neural Network

This paper proposes an efficient neural-network-based digital predistortion (DPD), named as envelope time-delay neural network (ETDNN) DPD. The method complies with the physical characteristics of radio-frequency (RF) power amplifiers (PAs) and uses a more compact DPD model than the conventional neural-network-based DPD. Additionally, a structured pruning technique is presented and used to reduce the computational complexity. It is shown that the resulting ETDNN obtained after applying pruning becomes so sparse that its complexity is comparable to that of conventional DPDs such as memory polynomial(MP) and generalized memory polynomial (GMP), while the degradation in performance due to the pruning is negligible. In an experiment on a 3.5-GHz GaN Doherty power amplifier (PA), our method with the proposed pruning had only one-thirtieth the computational complexity of the conventional neural-network-based DPD for the same adjacent channel leakage ratio (ACLR). Moreover, compared with memory-polynomial-based digital predistortion, our method with the proposed pruning achieved a 7-dB improvement in ACLR, despite it having lower computational complexity.

A 20.5 dBm Outphasing Class-F PA with Chireix Architecture at 3.5 GHz for RF Transmitter Front-end

An outphasing class-F power amplifier (PA) with Chireix architecture is presented in Global Foundry (GF) 0.13µm Complementary Metal Oxide Semiconductor (CMOS) technology. The proposed circuit is composed of two branch class-F PA and Chireix power combiner with a floating load. The designed outphasing amplifier can provide 20.5 dBm output power from 1.8 V power supply at 3.5 GHz with 52.9 % power added efficiency (PAE). Wideband Code Division Multiple Access (W-CDMA) signal is implemented as input signal to simulate ACPR and the adjacent channel leakage ratios (ACLRs) at ±5 MHz are -20.5 dBc/-20.7dBc. After DPD (Digital Pre-Distortion) ACLRs can achieve -44.5 dBc/-44.7dBc at ±5 MHz. Furthermore, the chip area including testing pads is 1.98*1.62 mm2.

Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

In this paper, a novel outphasing power amplifier (PA) based on class-E amplifiers with shunt capacitances and shunt filters is proposed. The new design provides high drain efficiency for both peak and back-off power levels. A mathematical model for the class-E power amplifier with shunt capacitance and shunt filter is presented. The proposed model enables derivation of load circuit parameters that provide optimum drain efficiency for the peak and back-off power levels using closed form mathematical expressions. Based on this model, an outphasing power amplifier is designed and subsequently implemented using microstrip transmission lines and a GaN HEMT devices. The fabricated power amplifier prototype is optimized for 2.14 GHz and provides drain efficiency of over 60% for back-off power levels up to 8.5 dB. The amplifier demonstrates a 44.3% drain efficiency for 64QAM OFDM modulated signal with 20 MHz bandwidth. Adjacent channel leakage ratio (ACLR) of −39.5 dB and error vector magnitude (EVM) of 0.9 % were achieved after the application of a memory polynomial linearization algorithm.

Digitally Assisted Harmonic Cancellation for Multi-Octave Filter-Less Transmitter

This paper presents and demonstrates the design of a filter-less transmitter architecture with digitally assisted harmonic cancellation. A neural network is used to model the harmonics as well as IMD for digital predistortion applications. This neural network-based harmonic modeling does not require any reference signal to be injected at the input of PA, thereby reducing the complexity in characterizing the harmonics. An in-house 10 W PA operating from VHF to L-band has been designed and characterized for its harmonic suppression. This PA is used along with agile RF transceiver AD9361 from Analog Device and Xilinx embedding platform using Zynq ZC-706 system-on-chip for implementing the entire transmitter. The receiver of AD9361 captures the nonlinearity of the PA in terms of harmonics as well as intermodulation distortion (IMD) components for modeling and predistortion. The proposed architecture can handle all types of distortions due to hardware as well as PA nonlinearity. Besides, it is also able to cancel the harmonics using a harmonic injection in the feed-forward configuration. This transmitter architecture has the advantages of being low cost, filter-less, wideband, frequency agile, reconfigurable and less bulky compared to the conventional scheme. The proposed scheme is demonstrated to transmit 5 MHz LTE signal at different frequencies over the range of 100 MHz to 400 MHz. In such a case, the second and third harmonics appear over the frequency range from 200 MHz to 1.2 GHz, which are within the amplification range of PA, yet they are suppressed without using any filter at the output. More than -40 dBc harmonic rejection is achieved over the entire operating range of this filter-less transmitter. The adjacent channel leakage ratio (ACLR) is always better than -45 dBc after applying digital predistortion.

Broadband Doherty Power Amplifier With Transferable Continuous Mode

In this paper, in-band continuous mode transferring (CMT) method is presented for designing broadband Doherty power amplifier (DPA). Specifically, transferable continuous mode, transferring between class-J continuum to class-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> continuum, is introduced into DPA at output back-off (OBO) power level for improving bandwidth and efficiency. For validation, a broadband DPA with operation mode transferring from continuous class-J to continuous class-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> is designed, fabricated and measured. Experimental results show the drain efficiencies (DEs) of the fabricated DPA are 46.3%-57.7% and 58.4%-69.1% at 6 dB OBO and peaking power levels over 1.7-2.6 GHz. The saturation power of this DPA is 43.1-45.2 dBm with a gain of 9.1-11.2 dB in the interested band. Furthermore, when the fabricated DPA is stimulated by a 20 MHz wideband signal with a peak-to-average power ratio (PAPR) of 7.05 dB at 2.4 GHz, the measured average power is 36.5 dBm with an average DE of 45.7%, and the measured adjacent channel leakage ratios (ACLRs) are -31.9 dBc and -50.4 dBc before and after DPD technique, respectively.

A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals

A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding −31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and −30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual output topology with an off-chip higher order output-matching network, combined with a positive feedback cross-coupled differential cascode amplifier stage. By using supply modulation and dynamic gate bias with an injection-locked PA, improved back-off efficiency, and acceptable out-of-band and in-band distortion is obtained. The integrated circuit occupies an area of 1.0 $\times $ 0.73 mm2 in standard 65-nm CMOS technology and uses a supply of 3.0 V.

Analysis on predistortion algorithm for improving adjacent channel leakage ratio of radio over fiber systems

AbstractNonlinear distortion introduced by optoelectronic components imposes serious limitations on the performance of radio over fiber (RoF) systems, such as dynamic range and adjacent channel leakage ratio (ACLR). In this article, we focus on the impact of digital predistortion (DPD) on the ACLR improvement in a wideband RoF system with multiple carriers. Three key factors, that is, the order of DPD algorithm, the initial phases of carriers, and the processing bandwidth of the predistortion module, are all taken into account in investigating the influence of predistortion on the ACLR performance of RoF systems. A preliminary experiment verifies the effectiveness of predistortion technique for improving the ACLR performance. Quantitative simulation results demonstrate that with the increase in the order of DPD algorithm, the ACLR performance can be significantly improved while the phase randomness within 10 carriers leads to an ACLR fluctuation up to 5 dB. The dependence of the ACLR improvement on the processing bandwidth of the predistortion module, which is very important in practical application, has also been quantitatively studied.

A Pulse-Modulated Polar Transmitter Using Direct Digital Synthesis for 5G NR Mobile Applications

This brief presents a pulse-modulated polar transmitter using direct digital synthesis (DDS) for 5G NR mobile phone applications. In contrast to the conventional radio-frequency transmitter that requires high-resolution digital-to-analog converters (DACs) to maintain signal fidelity, the proposed transmitter only needs high-speed but low-resolution DACs for DDS. A transmitter prototype was developed and tested with a 5G NR 20-MHz bandwidth signal at the carrier frequency of 836.5 MHz. The transmitter achieved the adjacent channel leakage ratio (ACLR) of −31.9 dBc using the 4 GS/s DACs with resolution of just 4 bits without the use of digital predistortion or other linearization techniques.

Analysis and Design of a Polar Digitally Modulated CMOS PA Based on Switched Constant-Current

Typical polar digital power amplifiers (DPAs) employ unit-cells operated in class-E or D−1, denoting a switched-resistance operation which degrades linearity. Besides introducing higher demand on digital predistortion (DPD), it also requires extra quantization bits, impacting the overall efficiency and system complexity. To address this, the present work makes use of an optimized constant-current cascode unit-cell which is combined with reduced conduction angle to achieve linear and efficient operation, while minimizing the effort on DPD and/or calibration. A design strategy is developed which focuses on the cascode bias voltage and transistor relative dimensions as design parameters, allowing cascode efficiency optimization without compromising linearity or reliability. A single-ended polar switched constant-current DPA is implemented in 180-nm standard CMOS. Continuous-wave measurements performed at 800 MHz demonstrate an output power of 24 dBm with a PAE of 47%. The DPA dynamic behavior was tested with a 64-QAM signal with 10 MS/s, achieving an average PAE of 20.9% with a peak-to-average power ratio (PAPR) of 8.7 dB and adjacent-channel leakage ratio (ACLR) = 40.34 dB. These results demonstrate comparable performance with the prior art while using only 6-bits clocked at 100 MHz baseband sampling frequency.

A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation

This article presents a fully integrated hybrid current- and voltage-mode three-way digital Doherty power amplifier (PA) in CMOS using a single supply with builtin large-signal phase nonlinearity compensation. The nonlinear phase responses in both current-mode digital PA (C-DPA) and voltage-mode digital PA (V-DPA) are theoretically analyzed, which are further leveraged to achieve the PA nonlinear phase compensation. To the best of our knowledge, it is the first time the amplitude modulation (AM)-phase modulation (PM) response in V-DPA is explained in detail. The PA exploits the lagging AM-PM distortion of C-DPA and leading AM-PM distortion of V-DPAs, resulting in built-in large-signal phase nonlinearity cancellation without phase pre-distortion. Moreover, the transformer-based Doherty output network provides active load modulation to both C-DPA and V-DPA, achieving a three-way Doherty PA for deep power back-off (PBO) efficiency enhancement without supply modulation. Finally, the 1.2-V single power supply for PA power cells and input drivers reduces supply complexity. As a proof-of-concept, the hybrid three-way digital Doherty PA is implemented in a 45-nm CMOS SOI process. The measurements show a 38.5% peak drain efficiency (DE), 22.4-dBm saturated output power (Psat), and 32.1%/18.7% DE at 3.4-/9.3-dB PBO, achieving ×1.25/×1.46 PBO efficiency enhancement over idealistic class-B PA PBO efficiency at 2.3 GHz. The measured AM-PM distortion is 4.7° which is state-of-the-art among DPAs with PBO efficiency enhancement. The hybrid digital Doherty PA supports 40-/10-MSym/s 64-quadrature amplitude modulation (QAM)/256-QAM at 15.3-/15.2-dBm average output power and 24.7%/23.2% average PA DE while maintaining error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) lower than -32/-32.1 dB and -30.6/-28.9 dBc without phase pre-distortion.

Watt-Level, Direct RF Modulation in CMOS SOI With Pulse-Encoded Transitions for Adjacent Channel Leakage Reduction

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch.

High Linearity Transmit Power Mixers Using Baseband Current Feedback

Transmit mixers frequently use Gilbert cells driven by common-source baseband amplifiers. Class-AB biasing is used in the latter for high efficiency, but this causes poor linearity. In this article, linearity is enhanced by using negative feedback to directly sense and linearize the baseband current flowing into the switching pair of the mixer. By suppressing both gate- and drain-induced nonlinearities, it achieves higher linearity and permits a higher power output compared to using replica devices of the common-source amplifiers in negative feedback. The technique is demonstrated using two prototypes: a 130 nm prototype designed for 1.9 GHz long term evolution (LTE) signals and a 65 nm LP prototype designed for Bluetooth basic data rate (BDR) and enhanced data rate (EDR) modes. The 130 nm prototype has an adjacent channel leakage ratio (ACLR) of −41.3/−40.4/−37.6 dBc for LTE5/10/20 at 11.7 dBm output, −148.6 dBc/Hz noise at 80 MHz offset for 10 dBm output, and −53.8 dBc CIM3 for 9 dBm output power. It consumes 335 mW from 3 V and 1.3 V supplies, including 79 mW in the LO buffers. The 4.4% efficiency represents 70% improvement over the state-of-the-art. The 65 nm prototype provides 4 dBm output power (EDR) while consuming 50.5 mW from 1.8 V.

A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation

High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc.

A Novel High-Pass Delta–Sigma Modulator-Based Digital-IF Transmitter With Enhanced Performance for SDR Applications

This brief presents a new transmitter architecture based on digital-intermediate frequency (IF) high-pass delta–sigma modulator (HPDSM). The proposed digital-IF transmitter topology utilizes a novel complex HPDSM topology to address the high quantization-noise power problem in Cartesian band-pass BPDSM and HPDSM-based digital-IF transmitters, without increasing the oversampling ratio of the signal or the clock rate of the system. To evaluate the performance of the new digital-IF transmitter system, a comparison with its Cartesian band-pass and high-pass counterparts, in terms of signal to noise and distortion radio (SNDR) and coding efficiency, was established. A simulation using 8 dB peak to average power ratio long term evolution signals with 1.24-MHz bandwidth showed that by integrating the proposed second-order complex HPDSM digital-IF in the transmitter, the power of the quantization noise is significantly reduced. The transmitter digital blocks were implemented on the BEEcube software-defined radio prototyping platform. The input signal is encoded by the new HPDSM topology and is up-converted and then fed to the inverse class-F switch-mode power amplifier. An overall efficiency of 12% was achieved by the proposed topology. Moreover, the output signal SNDR reached 37.8 dB and the adjacent channel leakage ratio at the lower and upper 1.25-MHz offset frequencies measured is equal to −35 dBc.

Digital Dual-Input Doherty Configuration for Ultrawideband Application

In this article, based on a dual-input configuration (DIC), a method for implementing ultrawideband or multiband load-modulated Doherty power amplifiers (DPAs) is proposed. The proposed DIC possesses two Doherty operating modes with respect to the working frequency. Each subamplifier of the DIC plays a changeable role versus frequency, changing from carrier to peaking or changing from peaking to carrier. A dual-input DPA working over 0.7–3 GHz (a relative bandwidth of 124%) is constructed for validating the proposed theory. Under continuous-wave signal excitation, experimental results illustrate that the fabricated power amplifier achieves a 6-dB back-off efficiency of over 40% across 0.7–3 GHz. The maximum output power of the fabricated DPA changes from 42.2 to 44.7 dBm across the whole working band. Meanwhile, a 20-MHz wideband modulated signal with a peak-to-average ratio of 6.04 dB is utilized to stimulate the fabricated DPA at 0.9, 1.8, 2.4, and 2.8 GHz. After digital predistortion, the measured adjacent channel leakage ratios are less than $-$ 50 dBc at four experimental frequency points.

Spectral Re-Growth Suppression in the FBMC-OQAM Signal Under the Non-linear Behavior of a Power Amplifier

Typically, the filter bank multicarrier with offset quadrature amplitude modulation (FBMC-OQAM) bears some impressive properties that make it popular as one of the substitutes to orthogonal frequency division multiplexing (OFDM) for the upcoming technology of broadband wireless communication systems. Although FBMC-OQAM preserves the multicarrier modulation (MCM) features, its spectrum usually suffers from impairments when subjected to the nonlinear behavior of a power amplifier (PA) which results in spectral re-growth. Due to the spectrum limitation and low energy efficiency foreseen in the forthcoming 5G networks, it is vital to confine the spectrum of the FBMC-OQAM signal within the allocated band of interest. In this paper, the suppression of the spectral re-growth experienced on the FBMC-OQAM signal due to the nonlinear distortion effects introduced by the PA is investigated. The crest factor reduction (CFR) method in combination with an adaptive digital pre-distortion (DPD) are used. The peak windowing technique based on sequential asymmetric superposition windowing (SASW) algorithm is used in the CFR part while the least square estimation with QR-decomposition (LSE/QR) has been used as the coefficient’s estimator and adaptation algorithm in the DPD part. The performance of the two combined techniques has been evaluated on SystemVue2018 simulation platform. The adjacent channel leakage ratio (ACLR) and the error vector magnitude (EVM) have been considered as the performance merits. The simulation results show that the proposed techniques significantly improve the spectrum, first by reducing the PAPR of the FBMC-OQAM signal by about 1.5dB. Secondly, the spectral re-growth has been reduced by about -45.74dB adjacent channel leakage suppression and the error vector magnitude measure has been obtained to be about 7.12%. (-22.95dB). These values lead to better average input power of the FBMC-OQAM signal and improvement in the spectral efficiency and they are in accordance with the 3GPP standard for wideband signals in nonlinear systems.