Adjacent Bits Research Articles

Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction

Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction

Modified Proficient Adjacent Error Correcting Codes

As the technology scales down, the soft errors manifested from faults appear in memories due to radiation effects. This paper suggests two decoding mechanisms using hamming bits, extended hamming bits and vertical parity bits applied on matrix codes. Among the proposed two ways of decoding, the method-2 induces less number of errors if the number of adjacent bits exceeds N/2 for N-bit data. Both decoding mechanisms are capable of correcting a maximum of N/2 adjacent errors in N data bits. The codes are modelled in Verilog HDL and are verified in Xilinx Vivado 2021.2 Tool for Zynq 7000 series FPGA. The results prove that the minimum bit overhead of 31.25% and maximum code rate of 76.19% can be achieved if 64-bits of data are processed at a time using proposed AEDAC codes but with a trade-off in terms of area.

Autonomous Navigation System of Indoor Mobile Robots Using 2D Lidar

Significant developments have been made in the navigation of autonomous mobile robots within indoor environments; however, there still remain challenges in the face of poor map construction accuracy and suboptimal path planning, which limit the practical applications of such robots. To solve these challenges, an enhanced Rao Blackwell Particle Filter (RBPF-SLAM) algorithm, called Lidar-based RBPF-SLAM (LRBPF-SLAM), is proposed. In LRBPF, the adjacent bit poses difference data from the 2D Lidar sensor which is used to replace the odometer data in the proposed distribution function, overcoming the vulnerability of the proposed distribution function to environmental disturbances, and thus enabling more accurate pose estimation of the robot. Additionally, a probabilistic guided search-based path planning algorithm, gravitation bidirectional rapidly exploring random tree (GBI-RRT), is also proposed, which incorporates a target bias sampling to efficiently guide nodes toward the goal and reduce ineffective searches. Finally, to further improve the efficiency of navigation, a path reorganization strategy aiming at eliminating low-quality nodes and improving the path curvature of the path is proposed. To validate the effectiveness of the proposed method, the improved algorithm is integrated into a mobile robot based on a ROS system and evaluated in simulations and field experiments. The results show that LRBPF-SLAM and GBI-RRT perform superior to the existing algorithms in various indoor environments.

High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM.

Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%.

A Novel Reversible Data Hiding Algorithm Based on Enhanced Reduced Difference Expansion

Reversible data hiding is a data-hiding technique which has the ability to recover the original version from stego-images after the secret information is extracted. In this paper, we propose a novel reversible data-hiding scheme based on an enhanced reduced difference-expansion technique. In the proposed scheme, the original image is divided into non-overlapping quad-blocks for embedding data. Then, to enhance the security, the secret bits are encrypted based on the encryption key and a symmetry-based strategy. To improve embedding capacity further, two adjacent encrypted bits are converted into a corresponding decimal digit. Difference expansion (DE) technique is applied to embed a decimal form instead of a binary version. Moreover, to maintain the good image quality, the enhanced reduced difference-expansion technique is used to reduce the original difference values so that it is suitable for decimal embedding. The experimental results demonstrated that the proposed scheme has achieved better performance in comparison with previous solutions.

Word-based encryption algorithm using dictionary indexing with variable encryption key length

<p>This paper proposes a new algorithm for text encryption utilizing English words as a unit of encoding. The algorithm vanishes any feature that could be used to reveal the encrypted text through adopting variable code lengths for the English words, utilizing a variable-length encryption key, applying two-dimensional binary shuffling techniques at the bit level, and utilizing four binary logical operations with randomized shuffling inputs. English words that alphabetically sorted are divided into four lookup tables where each word has assigned an index. The strength of the proposed algorithm concluded from having two major components. Firstly, each lookup table utilizes different index sizes, and all index sizes are not multiples of bytes. Secondly, the shuffling operations are conducted on a two-dimensional binary matrix with variable length. Lastly, the parameters of the shuffling operation are randomized based on a randomly selected encryption key with varying size. Thus, the shuffling operations move adjacent bits away in a randomized fashion. Definitively, the proposed algorithm vanishes any signature or any statistical features of the original message. Moreover, the proposed algorithm reduces the size of the encrypted message as an additive advantage which is achieved through utilizing the smallest possible index size for each lookup table.</p>

Dictionary Based Arabic Text Compression and Encryption Utilizing Two-Dimensional Random Binary Shuffling Operations

This paper developed Arabic text encryption and compression based on dictionary indexing algorithm. The proposed algorithm includes encoding the Arabic text utilizing Arabic words dictionary, mapping encoded binary stream to a two-dimensional binary matrix, utilizing randomized variable size encryption key, applying randomly binary shuffling functions on the two-dimensional matrix, and mapping back the two-dimensional binary matrix into a sequential binary stream. The decryption algorithm at the receiver side implements the encryption steps reversely, utilizing the encryption key and the shared Arabic word dictionary. In this dictionary, the words of the formal Arabic language are classified into four categories according to the word length and sorted alphabetically. Each dictionary category is given an index size that is large enough to fit all words in that category. The proposed algorithm shuffles adjacent bits away from each other in random fashion through utilizing randomized variable length encryption key, two-dimensional shuffling functions, and repetition loop. Moreover, the index size is selected not to be multiple bytes to destroy any statistical feature that may be utilized to break the algorithm. The proposed algorithm analysis concluded that it could be broken after 3.215∗109 years. Moreover, the proposed algorithm achieved a less than 30% compression ratio.

A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths

Multiplications have been commonly conducted in quantized CNNs, filters, and reconfigurable cores, and so on, which are widely deployed in mobile and embedded applications. Most multipliers are designed to perform multiplications with symmetric bit-widths, i.e., n - by n -bit multiplication. Such features would cause extra area overhead and performance loss when m - by n -bit multiplications ( m > n ) are deployed in the same hardware design, resulting in inefficient multiplication operations. It is highly desired and challenging to propose a reconfigurable multiplier design to accommodate operands with both symmetric and asymmetric bit-widths. In this work, we propose a reconfigurable approximate multiplier to support multiplications at various precisions, i.e., bit-widths. Unlike prior works of approximate adders assuming a uniform weight distribution with bit-wise independence, scenarios like a quantized CNN may have a centralized weight distribution and hence follow a Gaussian-like distribution with correlated adjacent bits. Thus, a new block-based approximate adder is also proposed as part of the multiplier to ensure energy-efficient operation with an awareness of the bit-wise correlation. Our experimental results show that the proposed approximate adder significantly reduces the error rate by 76% to 98% over a state-of-the-art approximate adder for Gaussian-like distribution scenarios. Evaluation results show that the proposed multiplier is 19% faster and 22% more power saving than a Xilinx multiplier IP at the same bit precision and achieves a 23.94-dB peak signal-to-noise ratio, which is comparable to the accurate one of 24.10 dB when deployed in a Gaussian filter for image processing tasks.

Fast Frequency Sweep Analysis of Passive Miniature RF Circuits Based on Analytic Extension of Eigenvalues

The construction of polar codes with code length $n=2^m$ involves $m$ layers of polar transforms. In this paper, we observe that after each layer of polar transforms, one can swap certain pairs of adjacent bits to accelerate the polarization process. More precisely, if the previous bit is more reliable than its next bit under the successive decoder, then switching the decoding order of these two adjacent bits will make the reliable bit even more reliable and the noisy bit even noisier. Based on this observation, we propose a new family of codes called the Adjacent-Bits-Swapped (ABS) polar codes. We add a permutation layer after each polar transform layer in the construction of the ABS polar codes. In order to choose which pairs of adjacent bits to swap in the permutation layers, we rely on a new polar transform that combines two independent channels with $4$-ary inputs. This new polar transform allows us to track the evolution of every pair of adjacent bits through different layers of polar transforms, and it also plays an essential role in the Successive Cancellation List (SCL) decoder for the ABS polar codes. Extensive simulation results show that ABS polar codes consistently outperform standard polar codes by 0.15dB--0.3dB when we use CRC-aided SCL decoder with list size $32$ for both codes. The implementations of all the algorithms in this paper are available at https://github.com/PlumJelly/ABS-Polar

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

Non-Binary Constrained Codes for Two-Dimensional Magnetic Recording

The two-dimensional magnetic recording (TDMR) technology promises storage densities of $10$ terabits per square inch. However, when tracks are squeezed together, a bit stored in the two-dimensional (TD) grid suffers inter-symbol interference (ISI) from adjacent bits in the same track, and inter-track interference (ITI) from nearby bits in the adjacent tracks. A bit is highly likely to be read incorrectly if it is isolated in the middle of a $3 \times3$ square; surrounded by its complements, horizontally and vertically. We improve the reliability of TDMR systems by designing two-dimensional constrained codes that prevent these square isolation patterns. We exploit the way TD read heads operate to design our codes, and we focus on TD read heads that collect signals from three adjacent tracks. We represent the two-dimensional square isolation constraint as a one-dimensional constraint on an alphabet of eight non-binary symbols. We use this new representation to construct a non-binary lexicographically-ordered constrained code where one third of the information bits are unconstrained. Our TD constraint codes are capacity-achieving, and the data protection is achieved with redundancy less than $3\%$ and at modest complexity.

Integer Codes Correcting Single Errors and Detecting Burst Errors Within a Byte

Correcting single and detecting adjacent errors has become important in memory systems using high density DRAM chips. The reason is that, in these systems, the strike of a single energetic particle can upset one or more adjacent bits. In this article, we present a simple solution for this problem based on integer codes capable of correcting single errors and detecting ${l}$ -bit burst errors confined to a ${b}$ -bit byte ( $1 {\, ). Unlike the classical approach, the proposed one does not rely on the use of dedicated encoding/decoding hardware. Instead, it uses the processor as both encoder and decoder. The effectiveness of such solution is demonstrated on a theoretical model of an eight-core processor. The obtained results show that it has the potential to be used in future DDR5 systems.

FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications.

Improving the performance of NRZ‐DPSK optical fiber networks using adaptive FSR in the receiver

AbstractIn this work, we consider the impact of spectral narrowing of 43Gb/s NRZ‐DPSK signals on the system performance. NRZ‐DPSK signals passing through reconfigurable optical add/drop multiplexer (ROADM) devices are subject to spectral narrowing due to the narrow bandwidth of ROADMs. For a system level analysis of this phenomenon, we model the ROADM devices as a bandpass filter, the bandwidth of which is deliberately decreased. The dependence of the system performance on the delay time between adjacent bits in the receiver is also investigated. It is shown that the performance of signals passing through ROADM devices can be improved with an appropriate delay line interferometer (DLI) for any amount of devices. These results were obtained by simulating the whole system performance using different values of the BPF bandwidth and FSR. We present a technique for finding the optimal FSR of DLI that allows for improving the performance of NRZ‐DPSK systems in the presence of spectral narrowing of the channel. Improved bit error ratio is achieved by using optimized FSR for each BW.

Research on novel modulation format Apol-FSK for optical transport network of 5G

Apol-FSK modulation format which combined the advantages of FSK and alternate polarization (APol) in 50 Gb/s optical transport network for 5G is proposed for the first time, the polarization switching between adjacent bits disables power interactions between them, resulting in a lower pulse interaction and a larger nonlinear tolerance. At the same time, the orthogonal polarization between bits is maintained over long transmission distance independently of PMD impacts in the transmission line. The transmission characteristics of Apol-FSK signal at 50 Gb/s compared with CSRZ-FSK and RZ-DPSK signal are investigated in this paper. Apol-FSK signal shows better transmission performance than CSRZ-FSK and RZ-DPSK signals, which could be one of the most potential solutions for future high-speed transmission systems.

ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories

Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is a major concern and is of decisive importance when a higher protection capability is required to tolerate multiple adjacent bit errors (burst errors). This article proposes the ECC-United Cache (EUC) architecture to improve the efficiency of EDCs/ECCs in set-associative L1 caches. EUC architecture extends the data protection granularity from a single word to multiple words by exploiting the parallel cache lines access, which is inherently available in the cache. As compared with the conventional architecture, EUC can be configured to provide: 1) the same protection capability with a significantly lower overhead, 2) a significantly higher protection capability with the same number of check bits, or 3) a trade-off between the former two features. Simulation results show that, when configured to minimize the overhead, EUC reduces the number of check bits by 69 and 75 percent in data-cache and instruction-cache, respectively. When configured to maximize the protection capability, EUC provides fourfold higher burst error detection/correction capability. Moreover, EUC is orthogonal to previous protection schemes and they can be redesigned based on the EUC architecture to further improve their efficiency.

Soft Error Tolerant Count Min Sketches

The estimation of the frequency of the elements on a set is needed in a wide range of computing applications. For example, to estimate the number of hits that a video gets or the number of packets in a network flow. In some cases, the number of elements in the set is very large and it is not practical to maintain a table with the exact count for each of them. Instead, simpler and more efficient data structures, commonly referred to as sketches, that provide an estimate are used. Among those structures the Count Min Sketch (CMS) is one of the most popular sketches. The CMS provides estimates that have one sided errors. In more detail, the CMS returns an estimate that is equal to or larger than the actual value. An update or check requires a small and constant number of memory accesses and the memory footprint is fixed and does not depend on the number of elements. The CMS relies on several arrays of counters that are stored in memory. Memories are prone to suffer soft errors that flip the contents of memory cells due for example to ionizing radiation. Therefore, it is of interest to study the impact that soft errors can have on the CMS estimates and to propose protection techniques that minimize their effect while requiring low overhead in terms of additional memory and circuitry. To the best of our knowledge this has not been done before. In this article, first the effect of soft errors on the CMS is evaluated by injecting errors. Then, in the second part a protection technique that does not require additional memory bits is presented and compared with the protection using a parity bit. In the last part of the article, the technique is extended to protect also against double adjacent bit errors.

Theory and performance analyses in quantum stream cipher based on bitwise NOT operation

Because of the realization of physical layer security, the Quantum Stream Cipher (QSC) is getting more and more attention. However, the error rate of each bit of ciphertexts is different from 0.5 for Eve in QSC. This drawback provides Eve with an opportunity to break QSC system possibly through some attacks, such as fast correlation attacks. Thus, to increase the bit error rate of ciphertexts in the higher bit positions to cope with this kind of attacks, this paper proposes a ciphertext mapping method based on Bitwise NOT Operation (BNO). According to parity of bases, BNO-based mapping performs bitwise NOT operation for some bit positions of ciphertext to expand the difference between adjacent bit positions of ciphertexts in QSC. Besides, BNO-based QSC can be directly employed in multi-bit plaintext mapping in QSC for different modulation formats, such as PSK/QSC and QAM/QSC. The security and transmission performance of QSC based on BNO are mainly investigated with different intensity ASE noises and the number of bases in optical back-to-back simulation. The simulation results demonstrate that bit error rate in each bit position of ciphertext is close to 0.5 by BNO method in QSC. Thus, BNO method can expand the impact of noise on the higher bit positions of ciphertext. In addition, BNO method has little influence on transmission performance of receiver in QSC system.

Modulation Code and Multilayer Perceptron Decoding for Bit-Patterned Media Recording

In a bit-patterned media recording (BPMR) system, reducing the spacing between adjacent bit islands in the down- and cross-track directions increases areal density; however, two-dimensional (2-D) interference comprising intersymbol and intertrack interferences degrades the system performance. To mitigate error patterns that increase the 2-D interference in BPMRs, 2-D modulation coding schemes have been proposed. In this letter, we present a modulation code and its decoding using a multilayer perceptron (MLP) for BPMRs. Modulation decoding using an MLP can achieve significantly better performance than that using the minimum Euclidean distance, which is generally used to decode received modulated data. Similarly, when comparing the system performance at the same user density, modulation decoding using an MLP at 3 Tb/in2 shows better performance than an uncoded system (partial response maximum-likelihood detector) at 2 Tb/in2.

Fast True Random Number Generator Based on Chaotic Oscillation in Self-Feedback Weakly Coupled Superlattices

Random numbers play a vital role in communications and cryptography. However, most existing true random number generators have difficulty in satisfying the requirements of high-speed communications due to their complexity and bulkiness, or low speed limitations due to equipment bandwidth. Then, the all-electron true random number generator was presented based on GaAs/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> As superlattices conducted under direct current bias at room temperature, which not only possesses the characteristics of miniaturization but also generates random numbers at rates up to the Gbit/s. However, the bit rate of random number generators based on superlattices is still much slower compared to chaotic laser random number generators. In order to generate higher-rate random numbers, we modified a DC-excited superlattice and then redirected the signal generated by the superlattice back into itself, thus introducing a self-feedback, and achieved a self-feedback superlattice true random number generator. This improvement makes the superlattice have a more detailed signal shape, a more effective signal amplitude, and with lower power consumption. Therefore, these advances made the self-feedback superlattice more suitable for generating random numbers. Moreover, we propose a new post-processing method, called the adjacent bits reversal exclusive-or. This method can reduce the sequence bias and correlation without discarding any random bit. The random number obtained by the self-feedback superlattice at a sampling rate of 10 GS/s passed the triple standard deviation test and the random number standard test (NIST SP 800-22), indicating that it possessed good statistical properties as a miniaturized random number generator.