Modified Proficient Adjacent Error Correcting Codes

Abstract

As the technology scales down, the soft errors manifested from faults appear in memories due to radiation effects. This paper suggests two decoding mechanisms using hamming bits, extended hamming bits and vertical parity bits applied on matrix codes. Among the proposed two ways of decoding, the method-2 induces less number of errors if the number of adjacent bits exceeds N/2 for N-bit data. Both decoding mechanisms are capable of correcting a maximum of N/2 adjacent errors in N data bits. The codes are modelled in Verilog HDL and are verified in Xilinx Vivado 2021.2 Tool for Zynq 7000 series FPGA. The results prove that the minimum bit overhead of 31.25% and maximum code rate of 76.19% can be achieved if 64-bits of data are processed at a time using proposed AEDAC codes but with a trade-off in terms of area.