Multiple Adjacent Bit Error Detection and Correction Codes for Reliable Memories: A Review

Abstract

The memories and registers are the critical components in a processor which are prone to errors like single bit upset or multiple bit upsets due to radiation effects. The error detection and correction codes are used to recover the memory from storing erroneous data or address which ensures reliability in operation. This review paper projects a brief of the codes that handle the errors in memories. The error detecting and correcting codes are capable of correcting errors from one bit to three adjacent bits. They operate based on the parity bits generated from data bits which are used to encode the data for transmission which are based on XOR gates. The decoding process varies for various methods which have syndrome calculation and error masking capabilities. The syndrome specifies the location of error if its value is non-zero. The error masking capability is achieved at a trade off with additional hardware. As the number of parity or redundant bits increases, multiple errors can be detected or corrected. The EDAC codes are assessed based on the metrics like the delay, number of redundant bits, number of errors detected, number of errors corrected, etc. Among the EDAC Codes, the matrix codes with QAEC decoding prove to be a better choice for memories.