Additional Switching Losses Research Articles

Difference Between the PWM and Standard DC Power Cycling Tests Based on the Finite-Element Simulation

PWM power cycling, which has complex control strategies and high testing costs, received a lot of attention in recent years due to the test conditions are closer to the application of power modules than standard DC power cycling. Therefore, the root difference of the failure modes and lifetime of IGBT power modules between DC and PWM power cycling is the concern in this paper, based on the finite element simulation. For stimulating the PWM power cycling with high accuracy and fast speed, an IPWM power cycling is proposed and verified by a simple model. Then an electro-thermo-mechanical coupled model of a single chip is established for comparison. Mainly focus on the current distribution, temperature distribution and stress distribution. The current distribution comparison results show no difference while a higher temperature gradient is shown in PWM power cycling due to the additional switching losses. However, the stress distribution results show chip solder layer is still the main failure mechanism both in DC and IPWM power cycling. Therefore, a conclusion can be obtained that there is no difference in failure mechanism and lifetime between DC and PWM power cycling. And the same bond wire failure and similar lifetime of DC and PWM power cycling tests further verify this conclusion.

Performance-based design of pseudo-sliding mode speed control for electrical motor drives

Sliding mode control (SMC) is a powerful technique for nonlinear systems with high-performance requirements, such as machine drives with power converters. However, sliding mode controllers often present chattering, undesirable in these applications, due to the additional stress and switching losses. Smooth functions can replace the switching function to overcome this issue, with the addition of integral sliding manifolds for steady-state error elimination. Recent studies have investigated the stability of these control systems, without providing optimum tuning methods. This study offers a tuning method for the boundary layer limit for electrical machine applications, which grants the ripple-free solution with the smallest steady-state error. Experimental results of an induction machine variable speed drive show that the controller tuning by the proposed method met the design requirements and that SMC is a feasible method for control of the application mentioned above.

Drain-Source Voltage-Controllable Three-Switch Active-Clamp Forward Converter for Wide Input/Output Voltage Applications.

Active-clamp forward converters are applied to various medium-capacity power systems because they have a relatively simple structure and are capable of zero-voltage switching. In particular, there is the advantage that a stable output voltage can be obtained by controlling the duty ratio of the power semiconductor switch even in applications with wide input and output voltage ranges. However, the voltage stress on the power semiconductor switches due to the application of active clamp is higher than the input voltage, especially as the duty ratio increases. A three-switch active-clamp forward converter is proposed, which can overcome such shortcomings and can reduce the voltage stress of the power semiconductor switches, but it causes an increase in the DC bias of the magnetizing current and the additional conduction and switching losses. Therefore, in this paper, a voltage-stress-controllable three-switch active-clamp forward converter that can utilize both advantages of the conventional active-clamp forward converter and three-switch active clamp forward converter is proposed and verified through a prototype for 800 W battery charger.

Auxiliary Power Module Elimination in EVs Using Dual Inverter Drivetrain

As electric vehicles compete with internal combustion engine cars, cost and weight savings remain central research objectives. The auxiliary power module, a dc/dc converter responsible for stepping down the power from the main traction battery to the auxiliary battery, has gained attention as a component where weight and cost savings can be achieved. With the auxiliary power module responsible for feeding everything from headlights to rising vehicular computational demands, these savings become evermore significant. This article introduces a system that integrates traction-to-auxiliary power conversion into the dual inverter drivetrain, leveraging typically underutilized degrees of freedom in the drive inverter to implement and control the dc/dc conversion eliminating the auxiliary power module. Due to the high level of integration, the proposed solution improves on existing literature by exclusively using the drivetrain’s active switches. Beyond capital savings and simplicity, this ensures no additional switching losses compared to regular driving operation. A mathematical model is motivated analytically and validated using computational simulations. A 1.2 kW prototype is constructed to validate the introduced concept experimentally.

A reduced switching frequency capacitor voltage balancing control for modular multilevel converters

Modular multilevel converter (MMC) is one of the most promising topologies in high/medium-voltage applications, but high switching losses impair system economy and reliability. For the high-voltage MMC with the nearest level modulation (NLM), there is usually high frequency and uncertain switching actions among submodules (SMs) in each arm, due to the traditional sorting based capacitor voltage balancing control method, which brings additional power losses. In order to solve this problem, the SM switching process and the capacitor voltage sequence of a MMC arm is analyzed, and then a method to predict the capacitor voltage convergence in the next control cycle is proposed in this paper. Based on the predicted voltage sequence, an improved capacitor voltage balancing method is proposed, which can significantly reduce the additional switching loss and improve the operating efficiency of the converter system. MATLAB/simulink simulation and RT-LAB based HIL test results verify the proposed method under different operating conditions.

Analytical Study of SiC MOSFET Based Inverter Output dv/dt Mitigation and Loss Comparison With a Passive dv/dt Filter for High Frequency Motor Drive Applications

Fast switching characteristic of wide bandgap devices enables high switching frequency of power devices and thereby, can facilitate high fundamental frequency operation of electrical machines. However, with the switching transition times in orders of tens of nanoseconds, the high dv/dt is observed across the switching device. The high dv/dt experienced by the switches, and consequently by the machine, can degrade winding insulations or bearings over a period of time. Therefore, it is imperative to maintain the dv/dt below recommended values depending on the machine insulation. The dv/dt across the devices can be adjusted by varying the gate resistance. A high value of gate resistance, however, introduces additional switching losses on the device. Using different dv/dt filtering techniques can also help to control the dv/dt on the machine terminals. These techniques do not increase the switching losses on the device. However, it introduces additional losses in the filter resistors and also increases the cost of the system. In this paper, an analysis based on the impact of gate resistance on the dv/dt across the machine, and the corresponding losses is carried out. An analytical dv/dt filter design strategy is proposed to limit the dv/dt to a particular value. With the proposed design scheme, the value of each filter component can be easily obtained, and filter losses can be estimated accurately. Lastly, a comparison is performed on the basis of efficiency between these two techniques.

Sawtooth-Carrier-Based Pulsewidth Modulation Method for Quasi-Z-Source Inverter With Zero-Voltage-Switching Operation to Reduce Harmonic Distortion and Inductor Current Ripple

This article proposes a novel sawtooth-carrier based pulsewidth-modulation (SCPWM) method for quasi-Z-source inverter (qZSI) with the zero-voltage-switching (ZVS) operation to reduce the total harmonic distortion (THD) and inductor current ripple. The conventional variable-duty pulsewidth-modulation (VDPWM) method has been being used for qZSIs because it causes the low switching loss. However, this method has the limitation not only to improve the THD of output current but also to reduce the size of inductor when it is applied to the qZSI. To figure it out, the proposed SCPWM method uses the sawtooth-carrier signal while keeping the benefit from the use of variable duty. In particular, the ZVS operation occurs whenever the edge of sawtooth-carrier signal is located in the time interval of shoot-through state. This allows to increase the carrier frequency of qZSI without any additional switching loss. Thus, both the THD of output current and the inductor current ripple can be reduced while keeping the high efficiency of system. The operating principle of the proposed SCPWM method is first explained in detail. Thereafter, its performance is mathematically analyzed and compared with that of conventional VDPWM method. Finally, its practical effectiveness is verified by the hardware experimental test.

1-kV Input 1-MHz GaN Stacked Bridge $\textit{LLC}$ Converters

In this article, a stacked bridge LLC converter with the split resonant tanks suitable for high input voltage is proposed to reduce the voltage stress of primary-side devices by half. The 650-V enhancement-mode gallium nitride high-electron mobility transistors (eGaN HEMTs) with much lower $R_{ds{\rm{(on)}}}$ and $Q_{g}$ are applied instead of 1700-V silicon carbide (SiC) mosfet s at 1-kV input to produce significantly reduced conduction loss and switching loss at 1 MHz. With eGaN HEMTs switching speed of 2.5 ns at 1-kV input, high dv / dt of 200 kV/ μ s causes large displacement current via the interwinding capacitance of the planar transformers, which distorts the resonant current seriously and causes zero voltage switching (ZVS) lost inducing additional switching loss and root mean square loss. The split resonant tanks solution is proposed to reduce the resonant current distortion to guarantee ZVS and voltage balance over the split capacitance. To reduce the interwinding capacitance, the noninterleaving type windings are proposed to minimize the displacement current from the primary side to secondary side of the matrix transformer. A practical engineering practice of a 1-MHz prototype with 1-kV input and 32-V/3-kW output is built. It achieves the peak efficiency of 96.2% at full load and power density of 107 W/in3, a size reduction of 69% compared to the 300-kHz SiC counterpart.

A three-dimensional active zero state PWM for common-mode voltage reduction of a three-phase four-leg voltage-source inverter

PurposeThis paper aims to investigate the common-mode voltage (CMV) issue of a three-phase four-leg voltage-source inverter. A new space vector modulation method, named as three-dimensional active zero state Pulse-width modulation (PWM) (3-D AZSPWM), is proposed to reduce the CMV level.Design/methodology/approachPWM is a general method to generate the switching signals of the power converters in order to obtain high-quality output voltages. However, the CMV produced by PWM methods has become a serious problem. 3-D AZSPWM is proposed to solve this issue. In 3-D AZSPWM, instead of using zero voltage vectors with high CMV level, appropriate complementary non-zero vectors are introduced to synthesize reference vector. The proposed method is classified into four types of AZSPWM1(a), AZSPWM1(b), AZSPWM2(a) and AZSPWM2(b) based on different complementary vectors chosen for each type. An extend software simulation using MATLAB/Simulink is performed to verify the superior performance of the proposed methods.FindingsCompared to other reduced CMV methods, the proposed method not only reduces the CMV but also retains the positive characteristics of the three-dimensional classical space vector PWM (3-D CSVPWM).Originality/valueThe proposed method does not suffer from linear modulation region limitation and also does not impose additional switching loss. Furthermore, calculated output voltage harmonic distortion factor illuminates acceptable quality of output voltage produced by the proposed method.

A New SVPWM for the Phase Current Reconstruction of Three-Phase Three-level T-type Converters

This paper presents a new space vector pulsewidth modulation scheme to reconstruct phase currents using neutral-point current sensing in three-level T-type converters (TLTTCs). For this purpose, zero vector and offset vectors are replaced with complementary active vectors. These active vectors do not affect the resultant output voltage and the voltage balance at the neutral point of TLTTCs. Hence, the pulsewidths of corresponding active vectors can be adjusted even at low speeds without much additional switching losses and low-frequency noise in the inverter. The modified switching patterns can easily be generated without significant computational complexity. The proposed method is experimentally verified using Texas Instruments TMS320F28335 and Spartan 6 controllers, on a custom designed T-type converter based on Fuji IGBT modules.

A New SVPWM Technique for DC Negative Rail Current Sensing at Low Speeds

Negative rail current sensing with the conventional space vector pulsewidth modulation (SVPWM) scheme imposes several challenges, particularly at low speeds and sector boundaries, where the pulsewidths of active vectors become narrow while the dc negative rail current becomes zero in null vectors (111) or (000). This paper presents a new SVPWM scheme by replacing null vectors with complementary active vectors such that the added vectors effectively cancel out each other, and the applied resultant voltage remains the same as in the conventional SVPWM. Hence, the pulsewidths of active vectors can be increased at low speeds without introducing additional switching losses, adding switching complexity, or introducing low frequency noise to the waveforms. Moreover, the proposed scheme reduces the system error caused by the deadtime of the switches with enlarged pulsewidths, enabling low-speed drive. The proposed technique is experimentally verified using a TMS320F28035 (Piccolo) microcontroller.

Valve Losses Evaluation Based on Piecewise Analytical Method for MMC–HVDC Links

This paper presents a new method based on piecewise analytical formulas to evaluate the valve losses of the modular multilevel converter based high-voltage direct current (MMC-HVDC) transmission systems. According to the generating mechanism, the total valve losses of the MMC are divided into three parts: 1) conduction losses; 2) essential switching losses; and 3) additional switching losses. Due to the large number of arm submodules in MMC-HVDC links, the harmonic components in the arm voltages and currents are omitted. Therefore, the conduction losses and the essential switching losses can be precisely represented by analytical formulas. The additional switching losses are described by an analytical upper limit. The case studies are performed on a 400-MW ±200-kV MMC-HVDC system under 12 typical operating conditions. Both the relative errors of the conduction losses and the essential switching losses between the analytical and the simulated results are within ±4%. The analytical upper limits cover almost all of the simulated results for additional switching losses. Finally, an acceptable number for the analytical method is described based on the simulation results, which proves the effectiveness of this method and clarifies the potential to take advantage of this method in engineering applications.

Active Gate Driver for Crosstalk Suppression of SiC Devices in a Phase-Leg Configuration

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

Integrated Inverter/Converter Circuit and Control Technique of Motor Drives With Dual-Mode Control for EV/HEV Applications

A new integrated circuit for motor drives with dual-mode control for EV/HEV applications is proposed. The proposed integrated circuit allows the permanent magnet synchronous motor to operate in motor mode or acts as boost inductors of the boost converter, and thereby boosting the output torque coupled to the same transmission system or dc-link voltage of the inverter connected to the output of the integrated circuit. In motor mode, the proposed integrated circuit acts as an inverter and it becomes a boost-type boost converter, while using the motor windings as the boost inductors to boost the converter output voltage. Moreover, a new control technique for the proposed integrated circuit under boost converter mode is proposed to increase the efficiency. The proposed control technique is to use interleaved control to significantly reduce the current ripple and thereby reducing the losses and thermal stress under heavy-load condition. In contrast, single-phase control is used for not invoking additional switching and conduction losses under light-load condition. Experimental results derived from digital-controlled 3-kW inverter/converter using digital signal processing show the voltage boost ratio can go up to 600 W to 3 kW. And the efficiency is 93.83% under full-load condition while keeping the motor temperature at the atmosphere level. These results fully confirm the claimed merits for the proposed integrated circuit.

Analysis of Soft-Switching Isolated Time-Sharing Multiple-Input Converters for DC Distribution Systems

This paper explores the feasibility of active clamping techniques in isolated time-sharing (TS) multiple-input converters (MICs). Additional losses caused by energy transfer from the leakage inductance in the isolating coupled-inductor into the input switches are addressed with a common active clamping leg for all input legs. An active clamping technique is applied to isolated TS-MIC to minimize the additional switching losses and voltage stresses on input legs. This paper also conducts an operational analysis of an isolated time-sharing dual-input single-ended primary-inductor converter (I-TS-DI-SEPIC) with the discussed active clamping technique. Zero-voltage switching can be achieved on the first-turned-on input leg and the active clamping leg with a proper driving strategy and well-chosen circuit parameter settings. Discussions on the effect of the active clamping technique to an MIC and the components stresses of the I-TS-DI-SEPIC with the active clamping technique have also been made to assist in the design of TS-MICs. Prototypes of the I-TS-DI-SEPIC with the active clamping technique have been built to demonstrate the performance in the application of split-phase dc distribution systems. Converter efficiency and voltage stresses are experimentally verified, showing that the active clamping technique achieves noticeable efficiency gains and component stress reduction.

Improved Asymmetric Space Vector Modulation for Voltage Source Converters with Low Carrier Ratio

This paper presents an improved asymmetric space vector modulation (ASVM) for two-level voltage source converters (VSCs) when the switching frequency is as low as nine times of line frequency. By adding two pulses in each line cycle when the fundamental voltage crosses zero, the total harmonic distortion (THD) of output current can be reduced significantly. The penalty of additional switching loss is very limited for high power factor operation. The applications of the improved ASVM in a single VSC or in two interleaved VSCs are shown, respectively. With the optimization of the duration and position of the additional pulses, the ac current THD can be reduced to as low as 50% for single VSC and even lower to less than 25% for interleaved VSCs systems. Such THD reduction has close relationship with space vectors' position, modulation index, and interleaving angle. Improved ASVM can also reduce the amplitude of circulating current in the interleaved VSCs, leading to smaller interphase inductors. Finally, the weights of total inductors needed to meet the same THD requirement are compared to demonstrate the benefits of improved ASVM when different pulsewidth modulation schemes are used. The analysis results are verified by experiments on a demo system.

Parallel Connection of Two Three-Phase Three-Switch Buck-Type Unity-Power-Factor Rectifier Systems With DC-Link Current Balancing

Connecting three-phase rectifier systems in parallel shows many advantages as compared to a single rectifier system with higher output power, such as higher reliability, smaller current and voltage ripple components, lower filtering effort, or higher system bandwidth. However, current unbalance or circulating currents can occur for modular design. In this paper, the parallel connection of two three-phase three-switch buck-type unity-power-factor pulsewidth-modulation rectifier systems is experimentally investigated for a 10-kW digital-signal-processor-controlled prototype. A space vector modulation scheme is employed showing all the advantages of an interleaved operation. Three control schemes for active dc-link current balancing are described employing an additional free-wheeling state that allows to influence the rate of change of the dc-link currents and can therefore be used for dc-link current balancing. The control schemes differ concerning control action and additional switching losses. Simulation and experimental results confirm the theoretical considerations: The dc-link current-balancing capability of the different control methods is compared, and the influence of the additional free-wheeling state on switching losses and operation behavior is investigated. The most advantageous control method, which employs a hysteresis controller and shows limited switching losses, is selected. The analysis of the mains behavior shows an improvement as compared to a single rectifier operation.

還流ダイオードの逆回復時間によるスイッチング損失の増加

還流ダイオードの逆回復時間によるスイッチング損失の増加