Additional Circuit Research Articles

Toward Optimized In‐Memory Reinforcement Learning: Leveraging 1/f Noise of Synaptic Ferroelectric Field‐Effect‐Transistors for Efficient Exploration

Reinforcement learning (RL), exhibiting outstanding performance in various fields, requires large amounts of data for high performance. While exploration techniques address this requirement, conventional exploration methods have limitations: complexity of hardware implementation and significant hardware burden. Herein, in‐memory RL systems leveraging intrinsic 1/f noise of synaptic ferroelectric field‐effect‐transistors (FeFETs) for efficient exploration are proposed. The electrical characteristics of fabricated FeFETs with low‐power operation capability verify their suitability for neuromorphic systems. The proposed system achieves comparable performance to the conventional exploration method without additional circuits. The intrinsic 1/f noise of the FeFETs facilitates efficient exploration and offers significant advantages: efficiency in hardware implementation and simplicity in adjusting the 1/f noise level for optimal performance. This approach effectively addresses the challenges of conventional exploration methods. The operation mechanism of the exploration method utilizing the 1/f noise is systematically analyzed. The proposed in‐memory RL system demonstrates robustness and reliability to the device‐to‐device variation and the initial conductance distribution. This work provides further insights into the exploration methods of RL, paving the way for advanced in‐memory RL systems.

Adding to the neuroimmune network model: A commentary on Nusslock etal. (2024).

Work by many groups demonstrate links between peripheral markers of inflammation and symptoms of depression. Here, Nusslock and colleagues present an update to their neuroimmune network model to incorporate a developmental lens. They propose that specific neural circuits may be responsible for causing heightened inflammation. One principal circuit includes the amygdala and prefrontal cortex and is proposed to be involved in threat detection. Thus, heightened threat sensitivity resulting from early life stress is suggested to cause increases in inflammatory signaling. Second, the authors suggest that reward circuits, including the striatum, may be targets of increased inflammation leading to symptoms of anhedonia. In this commentary, I add context to the model proposed by Nusslock etal., suggesting that taking a learning perspective and considering additional circuits, including the hippocampus and midline structures may be necessary to more fully account for the phenomena described by the authors.

Very high step‐down coupled inductor two‐phase buck converter with single magnetic element and inherent clamp voltage capability

AbstractThis paper proposed a new two‐phase high step‐down DC–DC converter is proposed. This converter is derived from the two‐phase series‐capacitor converter. The proposed converter replaces the series capacitor with a new structure that integrates Valley‐Fill circuit and coupled‐inductors concepts. This replacement can improve the voltage gain of the converter as well as a considerable reduction of diodes voltage stress. The proposed structure implements a dual‐phase buck using a single magnetic element. Also, the proposed structure inherently limits the voltage spikes due to the leakage inductance of coupled inductors without any additional clamp circuit. The proposed converter is analyzed, and design guidelines are provided. A 300–24 V prototype converter is implemented to justify the validity of circuit operation and the theoretical analysis.

Electrically‐Reconfigurable Extremely‐High Density Physical Unclonable Cryptographic Keys Based on Aurivillius Ferroelectrics

AbstractIn the era of information, emerging hardware security primitives, i.e., hardware random number generators and physically unclonable functions, hold profound promise for the establishment of exceptionally secure network information systems. Nonetheless, these potential solutions are constrained by inherent drawbacks, including the need for additional error correction circuits or algorithms, heightened susceptibility to environmental interference, and limited data density. This paper demonstrates the extremely high‐density, physical‐unclonable cryptographic keys by harnessing stochastically ferroelectric domain polarizations in Aurivillius ferroelectric material CaBi2Nb2O9 (CBNO). Ferroelectric polarization of CBNO nanodomains can serve as a robust source of physical unclonable entropy. Through the application of high‐speed voltage pulses, the inherent randomness of ferroelectric polarizations can be enhanced, thereby yielding cryptographic keys characterized by remarkable uniformity, uniqueness, and negligible environmental sensitivity. More importantly, the voltage pulse operations facilitate the configurability of the ferroelectric cryptographic keys with no correlation. An unprecedented data density of 435 Gbit µm−2 is therefore achievable with a miniaturized CBNO of less than 1 um2. Notably, the reconfigured keys successfully pass the National Institute of Standards and Technology random number tests without requiring additional post‐processing steps. Emanating from the inherent attributes of the material, these high‐density ferroelectric keys confer intrinsic advantages to information security, evincing substantial resistance to duplication or cloning.

CSA-based harmonic elimination controlled reduced switch multilevel inverter for standalone PV system

A standalone photovoltaic (PV) system has emerged as a clean energy solution for application in remote areas. To establish such a system a suitable converter is required for voltage boosting as well as to produce high-quality output as required by the load. To achieve this, multilevel inverters (MLIs) are the proven substitute in PV systems. A conventional MLI uses multiple sources and switches that increase the cost and complexity. To provide a complete stand-alone system solution that addresses this issue, reduced component switched capacitor (SC) based seven-level MLI is disclosed in this paper. A new crow search algorithm (CSA) based selective harmonic elimination (SHE) method is employed to estimate the switching angles. The dominant harmonic orders are removed from the 7-level SC-MLI output while the desired firing angles for the switches are evaluated. Using only seven switches, the circuit boosts the voltage to 1.5 times with the aid of self-balanced capacitors. Therefore, the circuit does not require an additional control circuit for voltage balancing. The overall system is designed in MATLAB/Simulink environment to test under different operating conditions. An experimental prototype of the 7-level SCMLI is also designed to validate the CSA-based SHE control and MLI performance in real time.

ДИНАМИКА УПРАВЛЕНИЯ ДВИЖЕНИЕМ ТРАНСПОРТНОЙ МАШИНЫ НА ЗАТЯЖНЫХ СПУСКАХ

The article provides a rationale for the need to develop an additional braking control system for a transport vehicle to limit the movement speed under the action of rolling forces and to protect the engine from exceeding the permissible speed, “overshooting” the speed. Design options for four systems that dissipate kinetic energy are considered, and the effectiveness of their use is assessed: in periodically switched off clutches in the transmission; in a hydraulic retarder, containing a rotor and a stator, where kinetic energy turns into heat and is dissipated into the environment; in two complex hydrodynamic transmissions, the design of which integrates a torque converter and a hydraulic retarder. In the first version of the system, kinetic energy turns into heat when the transmission clutches are periodically turned on and off; in the second option, energy transformation is carried out in the retarder circulation circle containing the rotor and the stator; in the third embodiment, in an additional circuit of the circulation circle of the working fluid of a hydrodynamic transmission, containing a pump, turbine, reactor wheels and an additionally introduced fourth wheel, which can serve as the stator; in the fourth version, the pump wheel of the torque converter can perform the additional function of the hydraulic retarder rotor, and the hydrodynamic transmission housing can function as the stator.

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

An extendable voltage boosting gain unit with a self‐balanced switched‐capacitors multilevel inverter using a single DC source

SummaryThis paper suggests an extendable voltage boosting gain unit (EVBGU) using switched‐capacitors SC with a single DC source. The proposed unit can be extended by a modular pattern to increase the output voltage levels and voltage‐boosting gain of the inverter. The main feature of this work is presenting a unit topology that utilizes multiple and modular subcells to achieve (double, quadruple, hexapole, octapule, etc.) voltage gain at the output by increasing the number of the subcells. All the subcells are connected only with one DC source. A positive feedback technique has been used to charge the capacitors of the unit using the accumulative charging voltage (ACV) method. Furthermore, all the capacitors are self‐balanced, so there is no need for any additional and complex control circuit. Moreover, to decrease the cost factor of the inverter, a low IGBT switch count is taken into consideration and no passive elements such as diodes are used in the proposed structure. The H‐bridge is connected to the unit to achieve bipolar voltage at the output. The operational analysis of the inverter is delineated in detail. A comparative study, with state‐of‐the‐art MLIs in different terms such as the number of components, the total standing voltage, and the gain, shows the particularity of the proposed EVBGU. The simulation of the proposed MLI is performed using PSCAD‐EMTDC software. The simulation results are validated experimentally.

Insights into additional lactone-based signaling circuits in Streptomyces: existence of acyl-homoserine lactones and LuxI/LuxR homologs in six Streptomyces species.

Acyl-homoserine lactones (AHLs), mediating pivotal physiological activities through quorum sensing (QS), have conventionally been considered limited to Gram-negative bacteria. However, few reports on the existence of AHLs in Gram-positive bacteria have questioned this conception. Streptomyces, as Gram-positive bacteria already utilizing a lactone-based QS molecule (i.e., gamma-butyrolactones), are yet to be explored for producing AHLs, considering their metabolic capacity and physiological distinction. In this regard, our study examined the potential production of AHLs within Streptomyces by deploying HPLC-MS/MS methods, which resulted in the discovery of multiple AHL productions by S. griseus, S. lavendulae FRI-5, S. clavuligerus, S. nodosus, S. lividans, and S. coelicolor A3(2). Each of these Streptomyces species possesses a combination of AHLs of different size ranges, possibly due to their distinct properties and regulatory roles. In light of additional lactone molecules, we further confirm that AHL- and GBL-synthases (i.e., LuxI and AfsA enzyme families, respectively) and their receptors (i.e., LuxR and ArpA) are evolutionarily distinct. To this end, we searched for the components of the AHL signaling circuit, i.e., AHL synthases and receptors, in the Streptomyces genus, and we have identified multiple potential LuxI and LuxR homologs in all 2,336 Streptomyces species included in this study. The 6 Streptomyces of interest in this study also had at least 4 LuxI homologs and 97 LuxR homologs. In conclusion, AHLs and associated gene regulatory systems could be more widespread within the prokaryotic realm than previously believed, potentially contributing to the control of secondary metabolites (e.g., antibiotics) and their complex life cycle, which leads to substantial industrial and clinical applications.

A novel switched-capacitor based multilevel voltage boost inverter for EV interface

ABSTRACT Lithium cells are connected in parallel and series to meet the current and voltage requirements in Electric vehicles (EV). Voltage and charge equaliser techniques are employed to protect the lithium cells. These equalisation circuits introduce the loss to the circuit, and the battery pack gets disconnected if any cell is faulty. Switched-capacitor converters have become an alternative to meet the voltage requirement. This article presents a voltage boost multilevel inverter configuration for electric vehicle applications. The proposed MLI features an inherent capacitor self-balancing capability and generates an output with a nine-level range. Algorithms for capacitor voltage balancing or additional sensor circuits are not required because of intrinsic self-balancing. For generating output levels, capacitors with a voltage source with an appropriate charging/discharging pattern are used. The proposed inverter doubles the output voltage for nine levels. A comparison of components, such as the number of semiconductors, diodes, gate driver circuits, and capacitors; system parameters such as voltage gain, blocking voltage, and TSV, is presented to demonstrate the advantages of the proposed MLI over recently developed topologies.

A novel IQ mismatch compensation method in wideband direct-conversion receivers.

Direct-conversion receivers (DCRs) have been widely used in recent years due to their small size and low power consumption. However, the mismatch between the in-phase (I) and the quadrature (Q) branches will seriously affect the performance of the DCRs. This paper proposes a novel blind compensation method to suppress the interference introduced by IQ mismatch. Based on the Hilbert transform, our proposed method can obtain the orthogonal signal of the I-channel signal by utilizing the Weaver architecture. Compared with traditional compensation methods, the main difference of the proposed method is that it ignores prior information, training sequences, and additional hardware circuits. Furthermore, the complexity of the proposed blind compensation method is low because no iterative operations are involved in the compensation process. The simulation results show that the proposed method has an excellent compensation performance, especially in wideband applications.

Response fitting in low-cost radiation sensors

To obtain low-cost solar radiation sensors with energy applications, small commercial photovoltaic cells have been adapted. With the purpose to evaluate the resulting thermal drifts, a temperature sensor has been connected to a small electronic circuit. The calibration curve provided by the cells supplier is not useful in this case because it is made for a constant 20ºC temperature. Besides, the additional circuit also affects the results. This work presents not only the design and implementation of the additional elements, together with the data acquisition system, but also the results of the calibration work, the fitting of new incident solar radiation functions regarding the temperature of the cell and the intensity of the resulting current, besides the validation of the results for four of these cells.

A dual source switched-capacitors multilevel inverter topology with extended voltage levels and voltage gain

The switched-capacitors multi-level inverters (SCMLI) are widely used in renewable energy resources for enhancing the quality and reliability of generated power. This paper suggests a new topology of extendable voltage levels and voltage gain units using switched capacitors SC with a dual DC source. The proposed unit can be extended by a modular pattern to increase the output voltage levels and voltage-boosting gain of the inverter. The main feature of this work is presenting a unit topology that utilizes multiple and modular sub-cells to increase the voltage gain at the output by increasing the number of the sub-cell components. A ternary relationship of the voltage magnitudes between the two asymmetrical DC sources is mandatory. Furthermore, all the capacitors are self-balanced, so there is no need for any additional and complex control circuit. Moreover, to decrease the cost factor of the inverter, a low IGBT switch count is taken into consideration and no passive diodes are used in the proposed structure. The H-bridge is connected to the unit to achieve bipolar voltage at the output. The operational analysis of the inverter is delineated in detail. A comparative study with state-of-art MLIs in different terms such as the number of components, the total standing voltage, the cost factor, and the gain shows the particularity of the proposed topology. The simulation of the proposed MLI is performed using PSCAD-EMTDC software. An experimental prototype is built to validate the simulation results.

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

A Hardware-Simplified Soft-Start Scheme for Current-Fed Full-Bridge DC-DC Converter

At present, the current-fed full-bridge DC-DC converter still faces two inherent defects, namely, the soft-start issue during the start-up process and the voltage spike issue in normal working conditions. In existing research, a large number of attempts have been reported to overcome these two inherent issues. However, the existing solutions are all based on both redundant soft-start circuits and snubber circuits, and two different circuits are required. As a result, the cost of the current-fed full-bridge DC-DC converter is high, especially because the soft-start circuits are only used during the start-up process. So, to reduce device redundancy, a hardware-simplified soft-start scheme is proposed in this paper. In the proposed scheme, the snubber circuit is reused for the soft-start process based on topology reconfiguration, avoiding additional soft-start circuits to reduce the cost of this DC-DC converter. In this proposed method, the current-fed full-bridge DC-DC converter is operated as the voltage-fed full-bridge DC-DC converter by always turning on the snubber switch during the start-up process. Then, the output capacitor can be charged by slowly increasing the output voltage of the H bridge. Then, when the output voltage is high enough, the current-fed full-bridge DC-DC converter is again operated in the current-fed mode to boost the voltage. Subsequently, the converter characters and control strategy were examined and analyzed. The experimental results verify the feasibility of the proposed hardware-simplified soft-start scheme for the current-fed full-bridge DC-DC converter.

Analisa Penambahan Jalur Circuit D pada Taxiway di Bandar Udara Internasional I Gusti Ngurah Rai - Bali

At every airport there is always something called a taxiway, the Runway Connecting Facility (taxiway) is a certain path within the airport location that connects the runway (runway) with the parking runway (apron) in the terminal building area and vice versa, consisting of an exit taxiway , parallel taxiway and high speed taxiway. Taxiway Functions as a connecting facility, so the taxiway in its planning must meet provisions such as the distance between the center line of the taxiway and the center line of the runway, width of the taxiway, wheel clearance, slope and visibility and finally the taxiway strip. In this research, qualitative methods were used to obtain results. By implementing additional circuits on the taxiway, it lightens the load on the CCR on circuit C and the cable route from the CCR on the south side is more efficient and easier to handle troubleshooting on the cable route. In the process of adding circuits to taxiway lights that need to be paid attention to is the preparation work for the application for making airport passes, the worker implementer makes a Method of Working Plan (MOWP) for detailed work and work methods, submits materials for approval. Work implementation must comply with regulations and Standard Operating Procedures (SOP).

Fault Identification in Modified Hybrid Digital Pulse Width Modulation using Triple Modular Redundancy

In this paper, the fault analysis is performed for the identification in the Modified Hybrid Digital Pulse Width Modulation by making use of the Triple Modular Redundancy method. The developed algorithm is real time implemented using the Xilinx Artix 7 FPGA device. The Modified Hybrid Digital Pulse Width Modulation is designed for the purpose of minimizing the Turn-ON and Turn-OFF delays in the triggering event of the generated Digital Pulse Width Modulation. Though additional compensatory circuits are added for the delay reduction, the area utilization is still low when implemented in FPGA device. Also, the Triple Modular Redundancy consists of three times of MHDPWM signal generation to check for the fault occurrence. For the sake of validating the fault identification, the majority voter circuit is used that could find the error at the earliest. The proposed method is checked for errors by inducing within the VHDL code and trailed with multiple duty cycle values. The proposed fault identification method is validated for VLSI parameters such as area, delay and power.

A Sub-1 ppm/°C dual-reference small-area bandgap reference comprising an enhanceable piecewise curvature compensation circuit

This paper presents a low-temperature coefficient (TC) dual-reference CMOS bandgap reference (BGR) for high-performance systems working under a wide temperature range. It consists of a correction approach to eliminate the high-order inaccuracy, in which an enhanceable curvature compensation circuit is adopted to extend the operating temperature range and generate reference voltages with sub-1 ppm/°C TC. In addition, a voltage level shifter (VLS) is used to generate the latter compensated reference voltage but no need for an additional compensation circuit. The proposed BGR designed in a 0.18-µm CMOS process has a simulated TC of 0.75 ppm/°C and 0.28 ppm/°C for the first and second reference outputs, respectively, over a wide temperature range of −50 °C to 130 °C. The proposed BGR occupies a 0.0079-mm2 silicon area. The overheads make the BGR appropriate to provide reference voltages in diverse chips with high-precision systems.

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons

Computation on a large volume of data at high speed and low power requires energy-efficient architectures for edge computing applications. As a result, scientists focus on memristive circuits and systems for area and energy efficiency. Spiking neural network (SNN) with bio-inspired spike-timing-dependent plasticity learning (STDP) is a promising solution for energy-efficient neuromorphic systems than conventional artificial neural network (ANN). Previous works on SNN with STDP learning primarily use memristor macro models, which are software-based and cannot give complete insight into circuit implementation challenges. Some reported works on SNN use memristive devices, which require additional fabrication steps. This article presents a full circuit-level implementation of the SNN system featuring on-chip training and classification using memristive STDP synapse in standard CMOS technology. A new learning rule using the modified STDP is implemented to simplify the weight modification process. It does not involve FPGAs, CPUs, or GPUs to train the neural network. The approach used in this paper to modify the weights does not require any additional combinational or digital circuits attached to the memristive synapse resulting in less consumption of area, energy and time. We demonstrated the complete circuit-level design, implementation and simulation of SNN with on-chip training and pattern classification using 180 nm CMOS technology. A comprehensive comparison of the proposed SNN circuit with the previous related work is also presented. To demonstrate the versatility of the CMOS synapse circuit for application scenarios requiring rate-based learning, we have tuned the pair-based STDP circuit to obtain Bienenstock–Cooper–Munro (BCM) characteristics and applied it to heart rate classification.