ADC Resolution Research Articles

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

This article describes a 4 × 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain-BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e-5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.

Digital Pulsewidth Modulation (DPWM) Using Direct Digital Synthesis

Wide-bandgap semiconductor power devices are being adopted to increase efficiency and switching frequency for power converters. This requires a demand for higher resolution digital pulsewidth modulation (DPWM) in digitally controlled power converters. This is because, in a digitally controlled dc–dc converter, steady-state limit-cycle oscillations can exist if the resolution of DPWM is less than the ADC resolution. This article proposes a cost-competitive, high-performance, functionally integrated with a small package-sized, a complete direct digital synthesis-based DPWM architecture to achieve a high resolution, linear, monotonic behavior, and extremely fast frequency hopping ability. This article presents a detailed analysis of the new DPWM architecture. Simulation and experimental results are presented to verify the analysis. This article also discusses the various advantages and numerous applications addressed by the proposed method.

Vector Modulator-Based Analog Beamforming Using the Least Euclidean Distance Criterion

In traditional multiple-input multiple-output (MIMO) receivers, radio frequency (RF) front-ends are exposed to interference as no analog spatial filtering is employed before the digital beamforming stage. Therefore the RF front-end is power-hungry, and analog to digital converters require a high dynamic range. In this paper, we consider an analog beamforming system in case of narrowband signals to cancel interference early in the analog domain, thus reducing the required ADC resolution. In contrast to existing analog beamformers with only phase shifts, our proposed design employs vector modulators where the coefficients can be selected from a set of weights with variable phases and amplitudes. We also propose an efficient and fast Euclidean distance algorithm to determine the analog beamformer coefficients while being suitable for realistic scenarios. Finally, an expression is introduced to estimate the interference rejection achieved by employing the proposed algorithm and a vector modulator in the RF domain. The introduced algorithm leads to considerable improvement in computational complexity by slightly sacrificing interference rejection.

Green Receivers for Massive MIMO Systems: A Joint Approach of Antenna Turn-Off and Multi-Level-Mixed-ADC Resolution Design

In this paper, two green receivers with antenna turn-off and multi-level-mixed-ADC resolution design are proposed for massive MIMO systems, such as 5G networks and Internet of Things (IOT). For practicality, a generic power consumption model for massive MIMO receivers, including ADC resolution, symbol detection, and receiver circuits, is considered. The two proposed green receivers are formulated to minimize power consumption with respect to their individual spectral efficiency (SE) constraints, which are aimed at obtaining the optimal solution of the number of active receive antennas and corresponding multi-level-mixed-ADC resolutions. First, the proposed schemes enable the number of active receive antennas to be equal to the number of receive antennas. Second, a variant of the decremental searching and dynamic programming (DSDP) method is conducted to obtain the correspondingly optimal candidate of the multi-level-mixed-ADC resolution. Third, decrease the number of active receive antennas by 1 and then conduct the variant of DSDP again to search the correspondingly optimal resolution candidate of multi-level mixed ADCs. Fourth, repeat these mechanisms to obtain all optimal multi-level-mixed-ADC resolution candidates for different numbers of active receive antennas. Last, the number of active receive antennas and the corresponding multi-level-mixed-ADC resolution candidate, which achieve the minimum power consumption, are chosen as the optimal solution. In addition, a novel mechanism for accelerating the work of searching the number of turn-off antennas has been designed in the proposed receivers. The simulation results show that compared to DSDP, the two proposed green receivers can provide the advantage of the adjustable flexibility of power consumption with different SE requirements.

Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.

Research on mechanical vibration monitoring based on wireless sensor network and sparse Bayes

Mechanical vibration monitoring for rotating mechanical equipment can improve the safety and reliability of the equipment. The traditional wired monitoring technology faces problems such as high-frequency signal pickup and high-precision data collection. Therefore, this paper proposes optimization techniques for mechanical vibration monitoring and signal processing based on wireless sensor networks. First, the hardware design uses high-performance STM32 as the control center and Si4463 as the wireless transceiver core. The monitoring node uses a high-precision MEMS acceleration sensor with a 16-bit resolution ADC acquisition chip to achieve high-frequency, high-precision acquisition of vibration signals. Then, the bearing vibration signal optimization method is studied, and the sparse Bayes algorithm is proposed as a compressed sensing reconstruction algorithm. Finally, the difference in reconstruction accuracy between this method and the traditional reconstruction algorithm is compared through experiments and the effect of this method on the reconstruction performance is analyzed when different parameters are selected.

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

A power and area efficient two-step hybrid voltage–time ADC achieves a 4-GS/s conversion speed and 39.9-dB SNDR in 28-nm CMOS. Two pipelined time-based converters (TBCs) with a thermometer capacitive DAC (CDAC) in the ADC lead to a high-speed and low-power operation. The pipelined architecture splits the full ADC resolution, thus relaxing the TBC complexity. The TBC consists of a voltage-domain comparator, a current-source-based voltage-to-time converter (VTC), and a ring oscillator (RO)-based time-to-digital converter (TDC) with feedforward and 2 $\times $ interpolation that achieves high conversion speed and good linearity simultaneously. The prototype ADC is fabricated in a standard 28-nm CMOS process with an active area of only 0.017mm2. The measured SNDR and SFDR are 39.9 and 47.8 dB with a Nyquist input at 4 GS/s. The FoMW and FoMS are 39.3 fJ/conv-step and 152.2 dB, respectively.

Improvement of m/z accuracy for linear matrix‐assisted laser desorption/ionization time‐of‐flight mass spectrometer

RATIONALE Linear MALDI-TOF MS is a widely used in analytical and biomedical applications. The use of delayed extraction increases the resolution, but the roughness of the matrix crystals and the target plate misalignment in order of a few μm cause substantial spread in the ion time-of-flight values and decrease mass accuracy. METHODS: The method of mass spectra correction based on the correlation of matrix fragments peaks in MALDI mass spectra was used. The experiments were performed with the MALDI-TOF instrument CMI-1600 built by Guangzhou Hexin Instrument Co., Ltd. SIMION 8.1 and MATLAB were used for ion motion simulations. Data analysis was done using the home built custom developed software and MATLAB. RESULTS: It was shown that the drift of peak position in the MALDI-TOF MS mass spectra depends linearly on the time-of-flight in a wide mass range. While using the linear correction of the time-of-flight scale, an increase in m/z accuracy of more than 10 times was achieved. The mass accuracy is limited by the resolution of the fast ADC used. CONSLUSION It is expected that the proposed method will significantly increase the dynamic range, since it becomes possible to sum up corrected individual mass spectra without significant loss of resolution. The time scale adjusting can be used both for the linear time-of-flight instruments and for the reflector systems of various configurations.

Mismatch suppression and noise reduction for SAR-ADC with Bayes estimation method

A statistical estimator based on Bayes Estimation theory is developed in this paper to simultaneously reduce capacitor mismatch and noise in a successive approximation register analogue-to-digital converter (SAR-ADC). Once the SAR-ADC has completed its quantization process, the residue voltage is available at the comparator input and can be estimated accurately using the Bayesian estimator. The ADC resolution is improved by subtracting the estimated residue from the digital output. The same technique of residue extraction is then used to estimate mismatches in the capacitive digital-to-analogue converter. A 15 dB improvement is observed in signal-to-noise-plus-distortion ratio by using the statistical estimator for a 10-bit SAR over a wide range of capacitance mismatch and ADC noise.

A Modified Nelder-Mead Algorithm for Photovoltaic Parameters Identification

Photovoltaic panels are prone to degradation after long outdoor exposure, which can be manifested in multiple forms. This phenomenon also causes an alteration of the panel's parameters. In this work, a heuristic search methodology based on the Nelder-Mead algorithm is applied in the estimation of photovoltaic panel parameters. Modifications that improve the performance of the method are also presented. The results of this modified Nelder-Mead algorithm are compared with the results of the classical method. A sensitivity analysis towards additive noise and ADC resolution is performed.

New Equivalent Model of a Quantizer With Noisy Input and Its Applications for MIMO System Analysis and Design

We propose a novel equivalent model for a quantizer with noisy input (the desired signal corrupted by measurement noise). It presents the quantizer output as a sum of the desired signal after it passes through a nonlinear element with a known equivalent transfer function and an equivalent additive white noise. The equivalent transfer function takes the form of a conditional expectation of the quantizer output given the desired signal portion of its input. The proposed model proves to be effective for the analysis and design of MIMO systems employing low-resolution quantizers (analog to digital and digital to analog converters, ADCs and DACs, respectively). We also demonstrate the efficacy of the model through several example applications for 1) the design of digital dither that mitigates the effect of DAC quantization error in a MIMO transmitter and significantly reduces the DAC resolution requirement; 2) the determination of the minimal ADC resolution required for operation of conventional MIMO receivers designed for infinite-resolution ADC arrays, without incurring significant performance degradation; and 3) the design of simple MIMO receivers (ML and MMSE) that mitigate the effect of insufficient ADC resolution, thereby extending the receiver SNR operating range without an undue complexity increase.

Fronthaul-Constrained Cell-Free Massive MIMO With Low Resolution ADCs

In cell-free massive MIMO networks, a large number of distributed access points (APs) provide service to a much smaller number of mobile stations (MSs) over the same time/frequency resources. The key idea is to use a central processing unit (CPU) to manage such a densely populated network of APs. This centralization helps reducing operational costs and eases implementation of joint power control and coherent signal processing through a proper orchestration of the functional split between the CPU and the APs. Cell-free massive MIMO networks, however, are often subject to stringent capacity requirements on the fronthaul links connecting the APs to the CPU and thus, low-resolution ADCs must be used to quantize the signals shared among CPU and APs. In this paper, analytical closed-form expressions for the achievable user rates on both the uplink (UL) and downlink (DL) of a fronthaul-capacity constrained cell-free massive MIMO network using low-resolution ADCs are obtained. These expressions, jointly with the use of theoretical models characterizing the fronthaul capacity consumption of different CPU-AP functional splits, allow posing max-min fairness power control optimization problems that can be solved using standard convex optimization algorithms. Numerical results show that, under fronthaul capacity constraints, CPU-AP functional splits where the precoding/decoding schemes are implemented at the APs are clearly outperformed by those functional splits in which, thanks to sharing CSI among APs and CPU, the precoding/decoding functions are implemented at the CPU. In contrast, if the limiting factor is the resolution of the ADCs used to quantize the samples to be transmitted on the fronthaul links, the preferred CPU-AP functional splits are those in which the baseband processing is performed at the APs. Moreover, they also reveal that in such functional splits there is always an optimal range of values of the UL fronthaul capacity fraction allocated to share the CSI.

A Case for Digital Beamforming at mmWave

Due to the heavy reliance of millimeter-wave (mmWave) wireless systems on directional links, beamforming (BF) with high-dimensional arrays is essential for cellular systems in these frequencies. Thus, performing the array processing in a power-efficient manner is a fundamental challenge. Analog and hybrid BF require few analog-to-digital and digital-to-analog converters (ADCs and DACs), but can only communicate in a small number of directions at a time, limiting directional search, spatial multiplexing, and control signaling. Digital BF enables flexible spatial processing but must be operated at a low quantization resolution to stay within reasonable power levels. This decrease in quantizer resolution distorts the received as well as the transmitted signal. To assess the effect of coarse quantization at the receiver, this paper presents a system level analytic framework based on a simple additive quantization noise model (AQNM). The analysis verified through extensive simulations reveals that at moderate resolutions (3-4 bits per ADC), there is negligible loss in downlink cellular capacity from quantization. In essence, the low resolution ADCs limit the high SNR, where cellular systems typically do not operate. For the transmitter, it is shown that DACs with 4 or more bits of resolution can support high order modulations, and do not violate the adjacent carrier leakage limit set by 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> Generation Partnership Project (3GPP) New Radio (NR) standards for cellular operations. In fact, our findings suggest that low resolution digital BF architectures can be a power-efficient alternative to analog or hybrid BF for both transmitters and receivers at millimeter-wave.

SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup

Although the CMOS-based CNN accelerators have achieved impressive progress, the memory wall issue and the high power density are still the major barriers for substantial improvement in energy efficiency and throughput. As an attractive alternative, recently the Resistive RAM-based accelerators have delivered significant breakthroughs by leveraging the in-situ computation. However, there are still some challenges, including the high computation complexity and the large energy overhead at the analog/digital interfacing circuits. In this work, we take advantage of the subword-based computation in the Resistive RAM-based accelerator to achieve energy saving and speedup. First, an encoding method is proposed for the weights and activations to reduce the energy consumption of the in-situ computation and the resolution requirement of ADC. Then the resolution of ADC is further optimized based on the distribution of the subword computation results. Furthermore, a dynamic quantization scheme is proposed to skip 67%–87% of the subword computations which outperforms the conventional quantization schemes. We fully investigate the influences of the encoding scheme and the layer-wise quantization range scaling on the performance of dynamic quantization. Finally, we demonstrate the effectiveness of the proposed algorithms under different hardware configurations and network complexities. A dedicated architecture, SubMac, is proposed to implement the above schemes. Experimental results show that the energy efficiency and the throughput are improved by 2.8–5.7 and 2.5–7.9 times, respectively, when compared with the state-of-the-art Resistive RAM-based accelerators.

BER performance analysis of coarsely quantized uplink massive MIMO

Abstract Having lower quantization resolution, has been introduced in the literature, to reduce the power consumption of massive MIMO and millimeter wave MIMO systems. Here, we analyze the bit error rate (BER) performance of quantized uplink massive MIMO employing few-bit resolution ADCs. Considering ZF detection, we derive a signal-to-interference, quantization and noise ratio (SIQNR) to achieve an analytical BER approximation for coarsely quantized M-QAM massive MIMO systems, by using a linear quantization model. The proposed expression is a function of the quantization resolution in bits. We further numerically investigate the effects of different quantization levels, from 1-bit to 4-bits, on the BER of three modulation types QPSK, 16-QAM, and 64-QAM. The uniform and non-uniform quantizers are employed in our simulation. Monte Carlo simulation results reveal that our approximate formula gives a tight upper bound on the BER performance of b-bit resolution quantized systems using non-uniform quantizers, whereas the use of uniform quantizers cause a lower performance. We also found a small BER performance degradation in coarsely quantized systems, for example 2–3 bits QPSK and 3–4 bits 16-QAM, compared to the full-precision (unquantized) case. However, this performance degradation can be compensated by increasing the number of antennas at the BS.

Fast multi channel acquisition system without dead time capable to measure oscilloscope-like signals.

Within the Baltic Sea Underground Innovation Network (BSUIN) project, we design and build a multichannel signal analysis and acquisition system. Our device can acquire signals from up to 32 detectors at the same time. Each channel has symmetric input, independent adjustable analog trigger, 10 MHz sampling rate, and 10 bits ADC resolution. Micro-controller (μC), FPGA, and micro-processor with Linux allow for different configuration of the system and for preliminary data analysis. In principle the signal’s wave-forms from each channel are stored in memory, and a pulse shape analysis can be performed. Independent power suppliers are provided for each channel. We are going to use this measuring system for neutron registration with large number of neutron detectors (helium proportional counters, scintillation neutron detectors, and charged particle scintillation detectors). Especially, measurements of simultaneous measurement of coherent signals from a number of neutron detectors is the purpose for this data acquisition system.

When Less Is More$\ldots$ Few Bit ADCs in RF Systems

Digitizing RF signals using few bit ADCs can provide system advantages in terms of reduced power dissipation, wider sampling bandwidth, and decreased demand for digital throughput. The diversity of established applications based on few bit ADCs, together with the recent surge of interest in the topic for 5G wireless communications and millimeter-wave radar, has created a need for practical design guidance governing their use in general RF systems. This paper, therefore, summarizes the state-of-the-art in few bit ADCs, comparing the dynamic range considerations involved with those of conventional RF receiver design. A simple analytic model for the monobit ADC is extended to multiple bits. Parametric analysis, independent of sampling considerations and system-specific signal processing, is used to illustrate the variation in the ADC output signal-to-noise-and-distortion ratio (SNDR) versus both the number of quantization bits and the input signal-to-noise ratio (SNR). At low and negative input SNR, increasing ADC resolution beyond 3-4 bits yields little advantage in output SNDR. Experiment confirms analytic predictions for the specific conditions under which the loss of signal fidelity due to quantization can be made negligible. In addition, parametric analysis of two-tone intermodulation distortion shows clear disadvantages to quantizing with <;4 bits in the presence of strong blockers. The results reported in this paper, which are general and independent of system application, can be used to customize the number of ADC bits in an RF system based on system-specific performance requirements for receiver dynamic range.

Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

In this work, we first provide an overview of the state of the art in mismatch error estimation and correction for time-interleaved analog to digital converters (TI-ADCs). Then, we present a novel pilot-based on-line adaptive timing mismatch error estimation approach for TI-ADCs in the context of an impulse radio ultra wideband (IR-UWB) receiver with correlation-based detection. We introduce the developed method and derive the expressions for both additive white Gaussian noise (AWGN) and Rayleigh multipath fading (RMPF) channels. We also derive a lower bound on the required ADC resolution to attain a certain estimation precision. Simulations show the effectiveness of the technique when combined with an adequate compensator. We analyze the estimation error behavior as a function of signal to noise ratio (SNR) and investigate the ADC performance before and after compensation. While all mismatches combined cause the effective number of bits (ENOB) to drop to 3 bits and to 6 bits when considering only timing mismatch, estimation and correction of these errors with the proposed technique can restore a close to ideal behavior. We also show the performance loss at the receiver in terms of bit error rate (BER) and how compensation is able to significantly improve performance.

Mu2e calorimeter readout system

The Mu2e electromagnetic calorimeter is made of two disks of un-doped parallelepiped CsI crystals readout by SiPM. There are 674 crystals in one disk and each crystal is readout by an array of two SiPM. The readout electronics is composed of two types of modules: 1) the front-end module hosts the shaping amplifier and the high voltage linear regulator; since one front-end module is interfaced to one SiPM, a total of 2696 modules are needed for the entire calorimeter; 2) a waveform digitizer provides a further level of amplification and digitizes the SiPM signal at the sampling frequency of $200\ \text{M}\text{Hz}$ with 12-bits ADC resolution; since one board digitizes the data received from 20 SiPMs, a total of 136 boards are needed. The readout system operational conditions are hostile: ionization dose of $20\ \text{krads}$, neutron flux of $10^{12}\ \mathrm{n}(1\ \text{MeVeq})/\text{cm}^2$, magnetic field of $1\ \text{T}$ and in vacuum level of $10^{-4}\ \text{Torr}$. A description of the readout system and qualification tests is reported.

Capacitor mismatch calibration method for SAR ADC with minimum area and power penalty

A novel capacitor mismatch calibration method is presented to compensate the capacitor mismatches in a successive approximation register (SAR) ADC. The method features a new weight-balancing split capacitive DAC which allows automatic extraction and calibration of the capacitor mismatches by itself. As a result, the ADC's resolution can be substantially improved with minimum area and power penalty. The calibration method was verified and implemented in a 14 bit, 10 kS/s SAR ADC, fabricated in a 0.13 µm standard CMOS process. The measured signal-to-noise-plus-distortion and spurious-free dynamic range are 72.7 and 86 dB after calibration with 13.6 and 21.8 dB improvements, respectively. The total power consumption is 15.2 µW at a 1.2 V supply voltage.