Adaptive Supply Voltage Research Articles

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.

A novel high-density dual threshold GNRFET SRAM design with improved stability

We propose a novel single-ended static random access memory (SRAM) design with nine graphene nanoribbon FETs (9-GNRFET) in this paper. Single-ended has an impact on density, delays, static noise margin (SNM) and power consumption. The proposed model is implemented in HSPICE as a library for 16 nm GNRFET technology. This HSPICE-compatible compact model provides accuracy while maintain compactness, and make possible efficient circuit level simulations of futuristic GNRFET-based SRAM cells design. Simulations at low supply voltage of 0.325 V have shown that proposed cell provides power saving 4.8 × as compared to a supply voltage of 0.7 V. The half-select free technique provides bit interleaving architecture, consisting of error-free operations with VDD down to 325 mV. The proposed architecture implemented in 16 nm low leakage GNRFET technology presents the scalability of these cells near threshed voltage region, which can significantly reduce power consumptions with 0.21µW. The proposed SRAM cell design is based on simulations and results are verified on GNRFET HSPICE-compact model. The proposed cell verified under process variation, and is demonstrated with write-assist, the impact of geometrical liability and adaptive supply voltage scaling.

Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM

We propose a single-ended disturb-free carbon nanotube field effect transistor (CNFET) based stable nine transistors (9T) SRAM cell using multi-threshold (multi-Vt) technology. Simulations of the CNFET 9T SRAM cell, using a CNFET HSPICE model, have shown advantages over the conventional Si-CMOS cell in terms of leakage power consumption, dynamic power consumption, stability, and delay. Due to higher carrier mobility and high ION/IOFF ratio makes the CNFET devices suitable for high-speed nanoelectronics applications. The disturb-free architecture and bit interleaving approach provide error-free operations at the low supply voltage. The proposed SRAM cell implementation for low leakage 16 nm CNFET technologies provides the possibility of high integration density which also significantly reduces 3.2 × power consumptions as compared to the conventional cell. The multi-threshold technology is capable of improving simultaneously the leakage current and dynamic power consumption. The proposed SRAM architecture is implemented with write-assist, adaptive supply voltage scaling and the impact of geometrical liability.

A High-Efficiency Integrated Multimode Battery Charger With an Adaptive Supply Voltage Control Scheme

A high-efficiency multimode battery charger with an adaptive supply voltage (ASV) control scheme is presented in this paper. The proposed battery charger includes a charging circuit and a dc–dc buck converter. The charging circuit automatically switches among trickle current (TC), constant-current (CC), and constant-voltage (CV) modes corresponding to the battery voltage while the buck converter with ASV control generates an ASV to closely track the battery voltage, leading to significant reduction in the power loss of the charging circuit. To further enhance the efficiency of the battery charger, zero-current detection and nonswitching control schemes are employed to decrease the power consumption of the buck converter in TC and CV modes. The battery charger was implemented with a 0.35- μ m CMOS 2P4M process. The experimental results are shown to verify the theoretical analysis of the proposed charger. The maximum efficiency of the overall system is 88.3%, and the maximum efficiency improvement between the proposed charger and the conventional linear charger with fixed supply voltage is up to 11.6%.

Adaptive supply and body voltage control for ultra-low power microprocessors

Adaptive supply and body voltage control for ultra-low power microprocessors

Efficient Wi-Fi Power Amplifier LTCC Module Using a Buck Converter With a Power Inductor Implemented in Ferrite-Filled PCB Technology

This paper presents a power amplifier module (PAM) that operates efficiently in low-power mode for IEEE 802.11g Wi-Fi applications. The PAM consists of a power amplifier (PA), a buck converter, and a power detector. Two packaging technologies were used to integrate the compact module: a low-temperature co-fired ceramic (LTCC) technology and a ferrite-filled printed circuit board (PCB) technology. The LTCC portion includes radio-frequency inductors, capacitors, transmission lines, and interconnection lines to minimize the overall size, while a power inductor for the buck converter is implemented in ferrite-filled PCB. The PA and the buck converter are designed in 2-μm InGaP/GaAs heterojunction bipolar transistor technology and 0.35-μm CMOS technology, respectively. The output power level is converted into a voltage by the power detector, and the voltage controls the buck converter, thereby optimizing the supply voltage of the PA. This adaptive supply voltage helps to improve the power-added efficiency (PAE) in the low-power regime while maintaining linearity. The PAM showed an error vector magnitude of less than 4% up to an output power of 22 dBm. The PAE is 8% and 11% at output powers of 11 and 16 dBm, respectively, representing respective improvements of 60% and 43%. The overall size of the PAM is 5×7.5×1.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

Adaptive Supply Voltage Management for Low Power Logic Circuitry Operating at Subthreshold

Adaptive Supply Voltage Management for Low Power Logic Circuitry Operating at Subthreshold

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

Monolithic Single-Pole Sixteen-Throw T/R Switch for Next-Generation Front-End Module

A broadband monolithic linear single-pole, sixteen-throw (SP16T) antenna switch has been designed and fabricated in 180 nm thin film SOI CMOS process, which is intended for the next generation multimode multiband (MMMB) cellular applications. The switch features the minimum 0.7 dB and average 1dB insertion loss, 0.1 dB compression point of 29 dBm and at least 33 dB isolation at all cellular bands for mobile front ends by applying distributed architecture and adaptive supply voltage generator. To the best of our knowledge, this work is the first demonstration of SP16T antenna switch with superior isolation and power handling capacities for most of the known cellular bands with satisfactory harmonic and intermodulation distortion performance on SOI. The simulated and measured results show excellent agreement.

Boostable Repeater Design for Variation Resilience in VLSI Interconnects

Process variations and circuit aging continue to be one of the main challenges to the power-efficiency of VLSI circuits, as a considerable power budget must be allocated to cushion timing variations. A design-time allocation implies uniform power consumption on all fabricated instances, even if many instances do not have strong variations. Adaptive design provides a power-efficient approach to variation tolerance, since it uses power only when the variations of a circuit instance are harmful. This paper is an effort toward supply voltage adaptation for variation resilience in VLSI interconnects. The main idea is a boostable repeater design that can transiently and autonomously raise its internal voltage rail to boost switching speed. The boosting can be turned on/off to compensate variations. The boostable repeater design achieves fine-grained voltage adaptation without stand-alone voltage regulators or an additional power grid. Since interconnect is a widely recognized cause of bottleneck in chip performance, and tremendous repeaters are employed on chip designs, boostable repeater has plenty of chances to improve system robustness. Experimental results indicate that our approach significantly outperforms existing techniques, including over-design, conventional adaptive supply voltage system, and online adjustable buffer.

Dual-Level Adaptive Supply Voltage System for Variation Resilience

VLSI circuits of the 45-nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV (dual-ASV) system for designs containing many timing critical paths. This system can simultaneously provide ASV at both coarse-grained and fine-grained levels, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in the presence of variations.

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

A new circuit style is proposed to tune the delay, subthreshold leakage (ISUB), and gate leakage (IG) of high fan-in multiplexer circuits, such as the FPGA Look-Up Table (LUT) and Switch-Box (SB), without increasing the Gate Induced Drain Leakage (GIDL) current or causing any reliability problems. In the proposed Adaptive Vgs (AVGS) style, Regular Threshold Voltage (RVT) transistors are replaced with the Low-VT (LVT) ones, but during the active-mode, new transistors have Vgs = - ΔV in the OFF and Vgs = VDD - ΔV in the ON conditions where ΔV is a new adjustable supply rail. AVGS can be a scalable replacement of the Adaptive Body Biasing (ABB) and Adaptive Supply Voltage (ASV) techniques in emerging manufacturing technologies that have very small body effect and cannot tolerate voltages higher than the nominal supply voltage (VDD) due to the reliability issues. Proposed technique is verified on silicon in the 90 nm technology and remarkable results are observed. AVGS can also be utilized to customize the FPGA delay-leakage trade-off. Area, leakage, dynamic power, and performance overheads are small.

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS

A new adaptive circuit design approach is proposed and analyzed employing independently biased back-gated Double-Gate MOSFET (DGMOSFET) devices. Threshold voltage tuning using back-gate of the DGMOSFET was compared with a conventional body-bias method. The technique is a promising solution to control the transistor's threshold voltage while reducing undesirable effects at the sub-50-nm device technology nodes. An automatic adaptive circuit for threshold voltage tuning was implemented using DGMOSFET devices in 45 nm CMOS technology. Simulation results show that this circuit compensates for static and dynamic variations. This adaptation approach using DGMOSFETs along with adaptive supply voltage scaling allows simultaneous optimization of power and performance according to application-specific workload and requirements. Simulation results using a 45 nm CMOS technology indicate that this adaptive circuit design can provide 50% higher performance for the same energy, or consume 40% less energy for the same performance. In contrast to conventional methods which only employ dynamic voltage scaling, adaptive tuning of threshold voltages reduces power consumption while maintaining its noise margin.

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Negative bias temperature instability (NBTI) in pMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guard banding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.

Variability compensation for full-swing against low-swing on-chip communication

Adaptive body bias (ABB) and adaptive supply voltage (ASV) are effective methods for post-silicon tuning to reduce variability on generic combinational circuits or microprocessor circuit sub-blocks. We focus in this work on global point-to-point interconnects, which are evolving into complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterisation of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the effectiveness of ABB against ASV when put at work on two on-chip point-to-point link architectures: a traditional full-swing and a low-swing signalling scheme for low-power communication. This work provides guidelines for the post-silicon variability compensation of these communication channels, while considering realistic layout effects. In particular, the implications of cross-coupling capacitance on the effectiveness of variability compensation are analysed in this work.

Error-Resilient Low-Power Viterbi Decoder Architectures

Three low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages without incurring timing errors. Power savings in this design can reach 58% and 44% with a 0.15 dB coding loss under reduced voltage operation and process variations, respectively, with adaptive supply voltage and adaptive body biasing applied to avoid timing errors. In the other two designs, we permit data-dependent timing errors to occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied to correct for these errors. Power reduction in these schemes is achieved by either overscaling the supply voltage [voltage overscaling (VOS)] or designing at the nominal process corner and supply voltage (average-case design). Two techniques are proposed to develop efficient estimators for error-correction and achieving increased robustness to timing based errors. The first is based on reduced-precision redundancy and the second on state clustering. The first can achieve up to 40% and 25% power savings under VOS and process variations with loss in coding gain of 1.1 and 1.2 dB, respectively, in a 130-nm CMOS process. The second can achieve up to 71% and 62% power savings under VOS and process variations, respectively, at a loss in coding gain of 0.8 and 0.6 dB, respectively. Under process variations, the designs achieve 16-33X improvement in bit error-rate (BER) performance at a signal-to-noise ratio (SNR) of 2 dB.

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

Design of adaptive supply voltage for sub-threshold logic based on sub-1 V bandgap reference circuit

This paper presents the design methodology to produce an adaptive supply voltage, which is used to drive digital sub-threshold logic system. Design guidelines to maintain constant speed and power via adaptive VDD regulation are presented first. Then the paper discusses modification of sub-1V bandgap reference (BGR) circuits using dynamic threshold MOSFET technique to provide the necessary adaptive reference voltage. Another well-known sub-1V BGR circuit using current mode technique is also fabricated and compared. Both circuits are implemented in CMOS 0.18μm technology. Empirical data from SPICE simulation and first order approximation techniques are used to derive analytical design models used inside BGR circuit. Measurement results of both the fabricated circuits show reference voltage output of 500mV range; which are in good match of SPICE simulation.

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 μm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction-for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was nossible.