A novel high-density dual threshold GNRFET SRAM design with improved stability

Abstract

We propose a novel single-ended static random access memory (SRAM) design with nine graphene nanoribbon FETs (9-GNRFET) in this paper. Single-ended has an impact on density, delays, static noise margin (SNM) and power consumption. The proposed model is implemented in HSPICE as a library for 16 nm GNRFET technology. This HSPICE-compatible compact model provides accuracy while maintain compactness, and make possible efficient circuit level simulations of futuristic GNRFET-based SRAM cells design. Simulations at low supply voltage of 0.325 V have shown that proposed cell provides power saving 4.8 × as compared to a supply voltage of 0.7 V. The half-select free technique provides bit interleaving architecture, consisting of error-free operations with VDD down to 325 mV. The proposed architecture implemented in 16 nm low leakage GNRFET technology presents the scalability of these cells near threshed voltage region, which can significantly reduce power consumptions with 0.21µW. The proposed SRAM cell design is based on simulations and results are verified on GNRFET HSPICE-compact model. The proposed cell verified under process variation, and is demonstrated with write-assist, the impact of geometrical liability and adaptive supply voltage scaling.