Abstract
In this chapter, a case study of six-transistor (6T) Single-Ended Static Random Access Memory (SE-SRAM) bitcell with an isolated read-current path and its word-oriented array organization, suitable for low-V DD and low-power embedded systems is presented. The SE-SRAM has a strong 2. 65 × worst-case read Static Noise Margin (SNM) compared to a standard 6T bitcell and equivalent to an 8T bitcell from existing literature. The previously proposed single-ended bitcell topologies and their advantages and disadvantages are also highlighted with respect SE 6T SRAM bitcell. The SE 6T bitcell and its word-orientation, and how it departs from the existing topologies are discussed in detail. A comparison of noise margins, power and performance with standard 6T and 8T SRAM bitcells is also presented.
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