Adaptive Body Bias Technique Research Articles

Push–pull based operational transconductor amplifier topologies for ultra low voltage supplies

This work presents an Operation Transconductance Amplifier with improved common mode rejection based in both Nauta’s and Vieru’s push–pull based OTAs operating at a 0.5 V power supply in the 180 nm CMOS process, with an additional biasing circuit that employs an adaptive body bias technique for calibration of output common mode voltage. Equal size CMOS push–pull pair inverter cells comprised by rectangular and trapezoidal transistor arrays are simulated and compared, showing that trapezoidal arrays designs have a higher DC voltage gain while rectangular arrays are more tolerant to process variability. Two new adaptive body bias circuits for CMOS circuits are proposed, which are used to minimize the inverter cells PVT variability and at the same time control the push–pull based OTAs common mode output voltage and transconductance. A schematic-level simulation of a hybrid Nauta–Vieru OTA prototype was run and achieved as result a differential voltage gain of 58 dB, a CMRR of 108 dB, a total power consumption of 375 nW, unity gain-bandwidth product of 100 kHz for a capacitive load of 10 pF, and a total area of 13,650 $$\upmu \hbox {m}^2$$ . The same OTA was fabricated and its DC transfer functions were measured, showing a maximum 52 dB voltage gain, 73 dB CMRR and $$11~\upmu \hbox {V/A}$$ transconductance at a 0.5 V voltage supply.

A low power current-reuse LC-VCO with an adaptive body-biasing technique

This work presents a low-power low-phase noise current-reuse LC voltage controlled oscillator (VCO) with an adaptive body-biasing technique that enhances the reliability of the proposed circuit under process, voltage, and temperature (PVT) variations. Furthermore, the supply voltage and power consumption of the proposed VCO are reduced by the start-up oscillation condition that is provided by the adaptive body-biased circuit. This property is in fact very interesting from the power management perspective. The proposed VCO works at carrier frequency of 1.8 GHz and draws the power of only 306 µW from a 0.9 V supply. It achieves phase noise of −123.36 dBc/Hz at 1 MHz offset and provides a figure-of-merit (FoM) of −193.61 dBc/Hz. The post-layout simulation results of designed VCO in 0.18 µm standard CMOS technology confirm the effectiveness of the proposed circuit.

DPFFs:C2MOSDirect Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

We propose two master-slave flip-flops (FFs) that utilize the clocked CMOS (C2MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness.C2MOSstructure improves the setup margin and robustness while providing full compatibility with the standard cell characterization flow. Further, the direct path shortens the logic depth and thus speeds up signal propagation, which can be optimized for less power and smaller area. Measurements from test circuits fabricated in 130 nm technology show that the proposed FF operates down to 60 mV, consuming 24.7 pW while improving the propagation delay, dynamic power, and leakage by 22%, 9%, and 13%, respectively, compared with conventional FFs at the iso-output-load condition. The proposed FFs are integrated into an8×8FIR filter which successfully operates all the way down to 85 mV.

NBTI and Process Variation Circuit Design Using Adaptive Body Biasing

VLSI circuits are increasingly affected by process variations as well as aging effects has become inevitable. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. The IC designed without consideration of process variation fails to do operation correctly Numbers of techniques has proposed to mitigate the effect of process and NBTI effect but have limitation Adaptive Body Bias technique is proposed which mitigate the effect of NBTI and process variation.

A Simulation Study of Colpitts Oscillator Reliability and Variability

Nanoscale CMOS reliability and process variation effect on the LC Colpitts oscillator has been examined. Mixed-mode device and circuit simulation is used to investigate the physical insight of impact ionization to the Colpitts oscillator. An analytical equation of phase noise as a function of offset frequency, transistor parameters, and body bias has been derived. The analytical predictions are in good agreement with ADS simulation results. An adaptive body bias to minimize process variation effect on the Colpitts oscillator has also been proposed. The adaptive body bias technique effectively reduces the hot electron effect and process variability on the Colpitts oscillator performance, as supported by Monte Carlo simulation results.

ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the ß-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits-from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 × 8 finite-impulse response filter fabricated in a 0.13-¿m technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios.

Design Techniques for a Low-Voltage VCO With Wide Tuning Range and Low Sensitivity to Environmental Variations

This paper presents design techniques for a low-voltage voltage-controlled oscillator (VCO) with a wide tuning range and low sensitivity to process, voltage, and temperature (PVT) variations. For wide tuning range, a switched tuning scheme is employed coupled with voltage-boosting techniques in a manner that improves the quality factor and tuning range of a switched capacitor array. To minimize the design overhead required for a robust VCO, an adaptive body-biasing technique is proposed, which relaxes the startup constraint and increases the VCO's immunity to PVT variations. The proposed VCO is implemented in 0.18-mum CMOS technology and operates at 2.4 GHz. It achieves phase noise of - 117 dBc/Hz at 1-MHz offset and a tuning range 20% while consuming 365 muW of power. The figure-of-merit with the tuning range is -197 dBc/Hz, which is the lowest among recent state-of-the-art low-voltage VCOs.