Push–pull based operational transconductor amplifier topologies for ultra low voltage supplies

Abstract

This work presents an Operation Transconductance Amplifier with improved common mode rejection based in both Nauta’s and Vieru’s push–pull based OTAs operating at a 0.5 V power supply in the 180 nm CMOS process, with an additional biasing circuit that employs an adaptive body bias technique for calibration of output common mode voltage. Equal size CMOS push–pull pair inverter cells comprised by rectangular and trapezoidal transistor arrays are simulated and compared, showing that trapezoidal arrays designs have a higher DC voltage gain while rectangular arrays are more tolerant to process variability. Two new adaptive body bias circuits for CMOS circuits are proposed, which are used to minimize the inverter cells PVT variability and at the same time control the push–pull based OTAs common mode output voltage and transconductance. A schematic-level simulation of a hybrid Nauta–Vieru OTA prototype was run and achieved as result a differential voltage gain of 58 dB, a CMRR of 108 dB, a total power consumption of 375 nW, unity gain-bandwidth product of 100 kHz for a capacitive load of 10 pF, and a total area of 13,650 $$\upmu \hbox {m}^2$$ . The same OTA was fabricated and its DC transfer functions were measured, showing a maximum 52 dB voltage gain, 73 dB CMRR and $$11~\upmu \hbox {V/A}$$ transconductance at a 0.5 V voltage supply.