Abstract
In this work a novel approach to optimize digital integrated circuits yield with regards to speed, dynamic power and leakage power constraints is presented. The method is based on process parameter estimation circuits and adaptive body bias (ABB) and/or adaptive supply voltage (ASV) performed by an on-chip digital controller. The associated design flow allows to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the estimation circuits used, the proposed design flow. An application case study, referring to an industrial 0.13 ?m CMOS process is used to compare ABB and ASV techniques. It is shown that ABB technique is particularly effective at high working temperatures and allows a stronger yield improvement with respect to the ASV technique. In the presented study, yields originally below 18% are improved to 83% by means of ABB alone and to 97% using ABB and ASV jointly.
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