Active Neutral Point Clamped Inverter Research Articles

Modulation and voltage balancing control of dual five-level ANPC inverter for ship electric propulsion systems

Open-end winding motors are used extensively in ship electric propulsion systems, in which medium-voltage high-power inverters are a critical component. To increase the system voltage and power density, a dual five-level active neutral-point clamped (ANPC) inverter is proposed herein to drive medium-voltage open-end winding motors for ship electric propulsion. Each phase of this inverter comprises two five-level ANPC bridges and all the phases are powered by a common direct-current link. A hybrid modulation method is proposed to control this inverter. The series-connected switches in all the five-level ANPC bridges are operated at the fundamental frequency, and the other switches are controlled with a phase-shifted pulse-width modulation (PWM), which can achieve a natural balance between the neutral-point voltage and flying capacitor voltages in a carrier period. A closed-loop capacitor voltage balancing method based on adjusting the duty ratios of the PWM signals is proposed. The neutral-point voltage and flying capacitor voltages can be controlled independently and balanced without affecting the output phase voltage. Simulation and experimental results are presented to demonstrate the validity of this method.

A Hybrid Active Neutral Point Clamped Inverter Utilizing Si and Ga2O3 Semiconductors: Modelling and Performance Analysis.

In this paper, the performance of an active neutral point clamped (ANPC) inverter is evaluated, which is developed utilizing both silicon (Si) and gallium trioxide (Ga2O3) devices. The hybridization of semiconductor devices is performed since the production volume and fabrication of ultra-wide bandgap (UWBG) semiconductors are still in the early-stage, and they are highly expensive. In the proposed ANPC topology, the Si devices are operated at a low switching frequency, while the Ga2O3 switches are operated at a higher switching frequency. The proposed ANPC mitigates the fault current in the switching devices which are prevalent in conventional ANPCs. The proposed ANPC is developed by applying a specified modulation technique and an intelligent switching arrangement, which has further improved its performance by optimizing the loss distribution among the Si/Ga2O3 devices and thus effectively increases the overall efficiency of the inverter. It profoundly reduces the common mode current stress on the switches and thus generates a lower common-mode voltage on the output. It can also operate at a broad range of power factors. The paper extensively analyzed the switching performance of UWBG semiconductor (Ga2O3) devices using double pulse testing (DPT) and proper simulation results. The proposed inverter reduced the fault current to 52 A and achieved a maximum efficiency of 99.1%.

A Switched Capacitor Based Seven Level Active Neutral Point Clamped (ANPC) Inverter Topology with Reduced Switching Devices

A Switched Capacitor Based Seven Level Active Neutral Point Clamped (ANPC) Inverter Topology with Reduced Switching Devices

Review of reduced‐switch multilevel inverters for electric vehicle applications

AbstractThis paper deals with the detailed review and comparative analysis of latest reduced switch multilevel inverter topologies for electric vehicle applications. The recent trends in reduced‐switch multilevel inverters are discussed. Detailed review of the reduced‐switch multilevel inverter topologies, their merits and demerits, and the comparative analysis based on component count, total harmonic distortion, and efficiency are conducted. This paper gives a detailed review of recent trends in reduced‐switch multilevel inverter topologies for electric vehicle applications. Switching pattern of the topologies is provided for better understanding of the inverter operation. Comparative analysis of the reduced‐switch inverter topologies based on the component count, total harmonic distortion of output voltage, and efficiency is also presented in this paper. Based on the comparative analysis, it is observed that the interleaved nine‐level flying capacitor multilevel inverter topology achieved the lowest output voltage distortion of 1.6%, which is within the acceptable limits of IEEE 519‐2014 standard. It is observed that the three‐level active neutral point clamped multilevel inverter topology achieved the highest working efficiency of 99.4%. This paper discusses the most recent trends in reduced‐switch multilevel inverters. A comprehensive review of the recent publications and a crisp comparative analysis of the different inverter configurations based on component count, harmonic distortion of output voltage, and efficiency are presented in this paper.

Averaged Modeling and SRF-Based Closed-Loop Control of Single-Phase ANPC Inverter

This article presents a dynamic averaged model of active neutral point clamped inverter (ANPCI). The proposed model helps in significant reduction of computational resources required for system-level studies in various applications which employ ANPCI as main power conversion stage. The average model derived in this article can consider the effect of various nonidealities in ANPCI, and also its capacitor voltage-balancing issues. The model is also modular in nature, i.e., it can be extended for an N-level ANPCI. PSCAD/EMTDC simulations and experiments are performed for steady-state and transient conditions to show that the averaged model developed in this article accurately predicts the steady-state and dynamic waveforms of ANPCI in both open-loop and closed-loop operations, even for large simulation time-steps. For the closed-loop operation, synchronous reference frame dq-based controller is developed and implemented in a digital signal processor. In addition, the strength of the model is demonstrated by comparing the simulation waveforms and computational times required for simulating an ANPCI-based solar PV system using switching circuit model and the proposed averaged model.

A new family of boost active neutral point clamped inverter topology with reduced switch count

A new family of inverter topology for active neutral point clamped (ANPC) is proposed. The traditional ANPC gives the output voltage of half the input voltage which necessitates the use of higher input dc-link voltage. To fix this problem, a floating capacitor is used to increase the voltage of the output, which decreases the dc-link requirement. Moreover, no sensors are needed to stabilize the floating condenser for the proposed topology, which minimizes inverter complexities. The neutral point is connected directly to the load terminals, which decreases the leakage current and makes it suitable for solar PV integration. Two modes of operation of the proposed topology have been discussed while considering the voltage of the floating capacitor used in the topology. Furthermore, two extensions of the proposed topology with generalized structure have also been provided in the paper. A detailed comparison with similar topologies has been provided. The level-shifted pulse width modulation technique has been used for the control of the proposed active neutral point clamped topology. In order to illustrate the idea of the proposed active neutral point clamped inverter, the theory of operation and analysis is accompanied by simulation, and experimental waveforms obtained from a laboratory prototype are provided.

LCL-Filter Design Based on Modulation Index for Grid-Connected Three-Level Hybrid ANPC Inverters

This paper proposes an LCL-filter design based on the modulation index for grid-connected hybrid active neutral point clamped (ANPC) inverters. The three-level hybrid ANPC inverter consists of silicon insulated gate bipolar transistors and silicon carbide metal oxide semiconductor field effect transistors to reduce the switching losses. LCL-filter parameters for the three-level hybrid ANPC inverter are calculated using the current ripple factor. The current ripple factor is affected by phase voltage, which varies according to the modulation index, and therefore the inductance on the inverter side must be considered with the modulation index. To design inductance on the inverter side, the output phase voltage and grid voltage are used to analyze the current ripple factor. The filter capacitor and the inductance on the grid side are designed based on the reactive power absorption and current ripple attenuation. The effectiveness of the proposed LCL-filter design method is validated via simulation and experimental results.

A safe commutation strategy based on LRCD snubber circuit for five‐level active neutral point clamped inverter

Spike voltage generated during the turn-off transient is one of the key threats to IGBT. When the traditional RCD snubber is applied in the five-level active neutral point clamped (5L-ANPC) inverter to clamp the spike voltage, a transient large current caused by the charging of the snubber capacitor will increase power losses and current stresses of IGBTs. This study proposes a LRCD snubber for the 5L-ANPC inverter. It can effectively suppress the spike voltages and the transient large currents of IGBTs, thus reducing the power loss. For the 5L-ANPC inverter, the traditional commutation method also poses a threat to IGBTs. Near the zero-crossing point of the output voltage, the traditional commutation method will cause the IGBTs that operate at the carrier frequency to withstand three times of the rated voltage. This study proposes a safe commutation strategy based on the LRCD snubber. When the output voltage passes through zero-crossing point, the proposed commutation strategy uses four transition switching states to avoid the breakdown of IGBTs induced by overvoltage. It can ensure that all the IGBTs operate in the safe operating area (SOA). Experimental results are presented to verify the validity of the proposed method.

Elimination of Abnormal Output Voltage in a Hybrid Active NPC Inverter

This article proposes a method to eliminate abnormal output voltages generated in three-level hybrid active neutral-point clamped (ANPC) inverters. The hybrid ANPC inverter is a topology in which silicon (Si) devices are replaced with silicon-carbide (SiC) devices in part from the conventional ANPC topology. The hybrid ANPC inverters have the advantages of high switching frequency and low power switching loss due to the SiC devices. In this hybrid ANPC inverter, abnormal output voltages occur when the polarity of the output pole voltage is changed from positive to negative. The cause of the abnormal voltages is the switching time difference between the Si and SiC devices, and it is various from a few nanoseconds to a few microseconds. These abnormal output voltages need to be eliminated as it leads to degraded output power quality in the hybrid ANPC inverters. The proposed switching method effectively eliminates the abnormal output voltages and reduces output current distortion. The performance of the proposed method is verified using a prototype of the new three-level hybrid ANPC inverter type through both simulations and experiments.

A High Efficiency and Low Cost ANPC Inverter Using Hybrid Si/SiC Switches

This paper presents a performance investigation and design optimization of a high efficiency three-level Active Neutral Point Clamped (ANPC) inverter topology using hybrid Si/SiC switches. It uses a modulation strategy that produces a cluster of low frequency switches commutating at fundamental line frequency (realized with Si IGBTs) and high frequency switches commutating at carrier frequency (realized with hybrid Si/SiC switches) to facilitate a tradeoff between the inverter efficiency and cost. A generalized Si/SiC current rating ratio optimization algorithm is presented for the hybrid Si/SiC switches based on the power loss profile of ANPC inverter. This algorithm determines the optimal current rating ratio between the Si IGBT and SiC MOSFET for the hybrid Si/SiC switches based on the inverter operating specification and Si/SiC gate control technique to achieve the best tradeoff between cost, loss and reliability. The performance of the proposed ANPC inverter system is investigated and compared with other similar ANPC inverter systems. The proposed ANPC inverter system achieves higher efficiency compared to an all Si IGBT based ANPC inverter system, all SiC MOSFET based ANPC inverter system, and other ANPC inverter systems consisting mixed Si IGBT and SiC MOSFET devices. On the other hand, the semiconductor device cost of the proposed ANPC inverter system is much lower than an all SiC MOSFET based ANPC inverter system and the mixed Si IGBT and SiC MOSFET based ANPC inverter systems while it is on par with an all Si IGBT based ANPC inverter system.

Capacitor Lifetime Extension in a Hybrid Active Neutral-Point-Clamped Inverter With Reduction of DC-Link Ripple Current and Common-Mode Voltage

This paper proposes a reduction method for DC-link ripple current and common-mode voltage (CMV) in a hybrid active neutral-point-clamped (ANPC) inverter. A Si and SiC hybrid ANPC inverter has been developed recently to overcome the extremely high cost of a full-SiC ANPC inverter. A hybrid ANPC requires much fewer SiC MOSFETs than a full-SiC ANPC inverter while providing a comparable power density. Voltage source inverters such as hybrid ANPC inverters utilize electrolytic capacitors, which have a large capacitance per volume, as a DC link. However, an electrolytic capacitor is one of the most vulnerable components in a power electronic converter due to its small allowable ripple current. A large ripple current flowing into the electrolytic capacitor generates a heat loss, which shortens the lifetime of the capacitor. Furthermore, the common-mode voltage (CMV) causes an undesirable leakage current and electromagnetic interference. The CMV depends on the pulse-width modulation of the voltage source inverters. The proposed method enhances the reliability of the hybrid ANPC inverter by reducing the DC-link ripple current and CMV simultaneously. The effectiveness and validity of the proposed method are verified through simulations and experimental results.

Co-Reduction of Common Mode Noise and Loop Current of Three-Level Active Neutral Point Clamped Inverters

The increased switching frequency and speed of silicon carbide (SiC) MOSFETs lead to higher power density of inverters, but meanwhile resulting in weak electromagnetic interference (EMI). The impedance balance technique is a good way to reduce the common mode (CM) noise by making the voltage across the line impedance stabilization network (LISN) as small as possible. However, a side effect of this technique is the generation of relatively large loop current that circulates in the inverter. It can cause additional losses and cost, which can be a factor that stops the increase of the switching frequency by SiC MOSFET. This article, for the first time, analyzes the relationship between the CM noise and loop current of the three-level active neutral point clamped (ANPC) inverter, and proposes a co-reduction method for both. First, the CM noise and loop current are clarified for the ANPC inverter, and the analytical models for both are established. The conflict between the CM noise and loop current is introduced with a specific case by the existing design method. Then a co-reduction method is proposed and elaborated, which can both suppress the CM noise and the loop current. The extra cost and volume by the proposed method are also analyzed and are negligible. The design guideline is further shown for clarity. Finally, the analysis and proposed method is validated by the experiment.

Si/SiC hybrid 5-level active NPC inverter for electric aircraft propulsion drive applications

Medium voltage DC(MVDC) system is considered as a promising technology to improve the efficiency and power density of electric aircraft propulsion(EAP) drives. To adapt to the MVDC voltage level and achieve high drive performance, a five-level active neutral point clamped(5L-ANPC) inverter consisting of three-level ANPC and flying capacitor circuits is investigated, which possesses higher voltage capability, lower output harmonics, as well as mitigated dv/dt and common-mode voltage. To fulfill the requirements of high-speed operation and pursue further enhanced efficiency and power density of the inverter for the next-generation EAP drives, Silicon Carbide(SiC) semiconductor devices are considered for implementing the 5L-ANPC inverter. However, the large commutation loops associated with certain switching states of the inverter lessen the benefits of configuring all the switches as SiC devices. As a result, a hybrid Si/SiC 5L-ANPC inverter is developed with a synchronous optimal pulse(SOP) width modulation strategy for controlling the switches in cell 2 and finite-control-set model predictive controller(FCS-MPC) for those in cell 3 of the inverter. Consequently, in the proposed topology, the SiC devices are merely used for the high-frequency switches in cell 3 and the rest of the low-frequency switches are configured with Si IGBTs. This Si/SiC hybrid ANPC inverter concurrently provides high efficiency and low implementation cost at high-speed operation mode. Simulation and experimental results are provided to verify the effectiveness of the proposed hybrid inverter.

A Novel Single-Stage Five-Level Common-Ground-Boost-Type Active Neutral-Point-Clamped (5L-CGBT-ANPC) Inverter

The conventional active neutral-point-clamped (ANPC) inverter inherits excellent high-frequency common mode voltage (CMV) mitigation ability but with a restricted voltage gain. This letter proposes a novel five-level ANPC inverter that is able to accomplish voltage-boosting within a single-stage dc–ac power conversion. A common ground in the proposed topology not only mitigates the high-frequency CMV but also enhances the dc-link voltage utilization. The proposed topology exhibits lower voltage stresses and higher compactness when compared with a conventional two-stage five-level ANPC inverter. The proposed inverter saves three power switches and one capacitor while enhancing the overall efficiency. Simulations and experimental tests have validated the overall operation, efficacy, and practicality of the proposed ANPC inverter.

Design and implementation of a new unity gain nine‐level active neutral point clamped multilevel inverter topology

Design and implementation of a new unity gain nine‐level active neutral point clamped multilevel inverter topology

Independent switching technique to remove abnormal output voltage in hybrid active NPC inverters

This paper proposes the independent switching technique to remove abnormal output voltage in hybrid active neutral-point clamped (ANPC) inverters. The hybrid ANPC inverter is composed by mixing silicon (Si) devices and silicon carbide (SiC) devices, unlike the conventional ANPC inverter which is generally composed of Si devices only. SiC devices provide low switching losses under a high switching frequency and a high withstand ability under high temperature compared with Si devices. Therefore, the hybrid ANPC inverter using SiC devices provides low power losses, high efficiency, and high reliability compared with the conventional ANPC inverters. In this hybrid ANPC inverter, abnormal output voltages are generated when the sinusoidal output current crosses the zero point. The abnormal output voltages are momentary pulses that must not be generated, and these pulses distort the output current and degrade the power quality. These pulses have two typical causes: one is from the switching operation time difference between switches, and the other is from deadtime. This paper proposes the independent switching technique to remove the abnormal voltages caused by the two reasons and verifies the proposed technique by simulation and experiment.

Soft switching circuit of high-frequency active neutral point clamped inverter based on SiC/Si hybrid device

Although the silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) is superior to the conventional silicon (Si) insulated gate bipolar transistor in terms of switching performance, the switching losses of SiC devices increase rapidly by hard switching when the switching frequency (fsw) increase to hundreds of kilohertz (kHz). This paper proposes an auxiliary zero-voltage-transition circuit to realize zero-voltage-switching for all of the high-frequency main switches of the active neutral point clamped (ANPC) inverter based on a SiC/Si hybrid device, and zero-current-switching for all of the auxiliary switches. Through soft switching, the switching losses and anti-parallel diode reverse recovery losses of high-frequency SiC MOSFET switches can be further reduced. First, the circuit topology and the operation principle of the soft switching are detailed followed by the design procedure of the parameters. Then, the efficiencies of hard switching and soft switching ANPC inverters are compared with fsw changing from 10 to 200 kHz. To further improve the efficiency of the soft-switching inverter, two improved methods are proposed. The two proposed methods are auxiliary switches paralleling the external diode and utilizing synchronous rectification technology. Finally, a 1 kW, up to 200 kHz frequency ANPC inverter has been built to validate the above analysis.

Improving DC-Link Capacitor Lifetime for Three-Level Photovoltaic Hybrid Active NPC Inverters in Full Modulation Index Range

This article presents a dc-link capacitor lifetime improvement method for three-level photovoltaic hybrid active neutral-point clamped inverters in full modulation index range. The capacitors are one of the components with vulnerable reliability in a power conversion system. The dc-link capacitor current ripples lead to temperature rise and wear-out failure of the capacitors. The accumulated thermo-mechanical damages from the temperature rise reduce the capacitor lifetime and reliability of the system. The proposed modulation method suppresses effectively the dc-link capacitor current ripple to improve the capacitor lifetime. In this article, the proposed method is discussed via a comparison with conventional space-vector pulsewidth modulation in full modulation index range. The modulation index range is divided into two regions, namely medium-vector modulation and hybrid modulation region. The capacitor lifetime is evaluated by the capacitor lifetime model according to the modulation methods and modulation regions. The effectiveness of the proposed modulation method is verified through simulation and experimental results.

Analysis and Design of a Novel Six-Switch Five-Level Active Boost Neutral Point Clamped Inverter

This article presents an analysis and design of a new boost type six-switch five-level (5L) active neutral point clamped (ANPC) inverter based on switched/flying capacitor technique with self-voltage balancing. Compared to major conventional 5L inverter topologies, such as neutral point clamped, flying capacitor, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. Whilst reducing the dc-link voltage requirement, the number and the size of the active and passive components are also reduced without compromising the reactive power capability. The analysis shows that the proposed topology is suitable for wide range of power conversion applications (for example, rolling mills, fans, pumps, marine appliances, mining, tractions, and most prominently grid-connected renewable energy systems). Experimental results from a 1.2 kVA prototype justifies the concept of the proposed inverter with a conversion efficiency of around 97.5% ± 1% for a wide load range.

PWM Strategy for MW-Scale “SiC+Si” ANPC Converter in Aircraft Propulsion Applications

In this article, an improved pulsewidth modulation (PWM) strategy is introduced for three-level active neutral point clamped converters based on a hybrid configuration of silicon carbide (SiC) mosfets and silicon (Si) insulated gate bipolar transistor (IGBTs). Compared with the conventional PWM strategies in the literature, this proposed PWM strategy enables the SiC switches only to interface with small commutation loops, thus the turn-off voltage overshoots caused by the parasitic loop inductance and high <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di</b> / <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</b> are much lower. Soft switching is achieved across all the IGBTs, and the switching losses of the converter only dissipate from the SiC mosfets, leading to high efficiency of the converter. Also, with this improved PWM strategy, the conduction loss at zero voltage output of this converter is reduced due to the turn-on of two parallel conduction paths. Furthermore, this proposed PWM strategy can protect the body diodes of the SiC mosfets from conducting large load current. All these advantages with the proposed PWM strategy are experimentally verified in a megawatt-scale three-phase three-level “SiC+Si” hybrid active neutral point clamped inverter developed for electric aircraft propulsion applications.