Active Inductor Research Articles

An Inductor‐Less Zero‐IF Down‐Conversion Mixer With Low Flicker Noise and High Conversion Gain

ABSTRACTThis paper presents a novel active inductor (AI) to improve the performance of a down‐conversion active mixer in terms of conversion gain (CG) and flicker noise. The proposed AI exhibits negative resistance and partially flat inductance over a wide frequency band of 0.5–4.5 GHz. The effect of inserting the AI between the source of the switching quad of a Gilbert cell mixer is theoretically analyzed. The proposed inductor‐less mixer, designed to operate at a 2.4‐GHz RF input frequency and a 10‐MHz IF output frequency, employs current reuse and self‐forward body bias (SFBB) techniques. The proposed circuit is simulated in Cadence Spectre‐RF using RF‐TSMC 0.18‐μm CMOS technology. Post‐layout simulations demonstrate that the proposed AI significantly reduces flicker noise by over 23 dB at an IF output frequency of 1 kHz and improves the CG by over 16 dB at an RF frequency of 2.4 GHz. The proposed mixer achieves a CG of 37.6 dB and a flicker noise corner frequency of 6 kHz. Additionally, it exhibits a third‐order intermodulation intercept point (IIP3) of −5.2 dBm and a double‐sideband noise figure (DSB‐NF) of 6.1 dB at the IF output frequency of 10 MHz. Operating with a 1.5‐V supply, the proposed mixer consumes 10.6 mW of power.

INCAPE23-A Fully Differential Active Inductor with Cascode Current Mirror Using 0.18-um Technology for RF Frequency

This paper introduces a fully differential CMOS active inductor integrated with a cascoded current mirror, tailored for applications within the RF frequency range. The active inductor design is meticulously realized using CMOS 0.18-µm technology. The circuit implementation comprises a fully differential cross-coupled pair of transistors, strategically employed to impart negative feedback, thereby enhancing the quality factor (Q). The cascoded current mirror functions as a pivotal biasing component, facilitating control over the current source to modulate negative feedback and Q factor tuning. Simultaneously, two resistors integrated into the differential structure are crucial in managing the frequency spectrum. Simulation results substantiate a Q factor of 16k, coupled with an inductance of 14 nH, prominently achieved at 3 GHz frequency. Additionally, the objective of achieving a robust Q factor at 3.5 GHz, amounting to 500, is successfully realized. Noteworthy is the adaptability in achieving a frequency range spanning 2 GHz to 3.6 GHz by manipulating resistor values. Furthermore, the study observes that manipulation of supply voltage and current source enables the tuning of Q factor values from 70 to 16k. A performance assessment, juxtaposed with previously published works, underscores the viability of the proposed active inductor for applications within the gigahertz frequency range of RF.

INCAPE23-Design of Class E CMOS Power Amplifier with Integrated Active Inductor for 5G Applications

This paper presents a design of class E power amplifier (PA) with integrated active inductor for 5G applications. A high Q-factor active inductor (AI) is proposed utilizing CMOS 0.18-µm technology. A Gyrator-C based is employed to realize an active inductor with a double cascode resistive feedback configuration. The biasing voltage of 1.21 V, current source of 0.5 mA and supply voltage of 2.5 V is used. In order to obtain high efficiency, the proposed AI is implemented in a class E power amplifier by replacing on of the spiral inductors. According to the simulation results, the proposed AI can reach a high Q-factor of 50,000 and an inductance of 2.03 nH at 3.5 GHz. The power added efficiency (PAE) of CMOS class E PA with integrated AI, according to simulation result, is 72 % at 3.5 GHz. The intended PA's PAE was dramatically raised by the class E AI that was built.

Current Feedback Operation Amplifier Based on Floating Passive and Active Inductors in Filter Applications

This paper proposes using current feedback operation amplifiers (CFOAs) as an active filter in creating floating passive and active inductance simulators is a versatile and efficient solution for circuit design. CFOAs are popular for their high slew rate and wide bandwidth which makes them ideal candidates for applications demanding rapid response time alongside high frequencies. It is possible to customize these simulated inductances for different design specifics by changing certain external resistor values. The circuit comprises a trio of CFOAs, an earthed capacitor and three resistors, thus making it quite simple to put into practice at a cheap price. Experiments and LTSPICE simulations have been conducted to examine the performance of the circuit, and closely confirmed theoretical expectations. In other words, this confirms the trustworthiness and preciseness of the introduced floating active inductance simulator. Voltage-mode band-stop filtering is one real-world scenario where this circuit is used. This indicates that our proposed technique can have more applications than one in circuit design. This is further proof that our idea can be used in other circuits as well. In conclusion, using CFOAs in active filters for building a grounded passive active inductance simulator is a solid and effective answer to circuit designers. This makes it an appealing choice for numerous applications because of its simplicity in designing the network as well as its high performance and customizability. Circuit design and application can be greatly improved if more study is done in this field.

A compact and tunable active inductor-based bandpass filter with high quality factor for Wireless LAN applications

A fully-differential compact and tunable second-order bandpass filter (BPF) with high quality factor using a novel active inductor (AI) has been proposed for 3.6 GHz WLAN applications. The proposed AI employs a differential amplifier as a feedforward transconductor and a common-source (CS) transistor as a feedback transconductor in a symmetrical configuration. The combination of a cascode scheme and a resistor in the feedback path enhances the quality factor of the AI, thereby increasing the mid-band gain of the BPF. In order to achieve independent tuning of both the center frequency and mid-band gain of the BPF, a varactor capacitor is utilized. The proposed second-order BPF is designed with a center frequency and a bandwidth of 3.675 GHz and 10 MHz, respectively. Post-layout simulation, process corner, and temperature sweep analysis results are conducted with 65 nm CMOS technology at 1.2 V supply voltage. The proposed filter has a tuning range of 3.655–3.695 GHz and attains a mid-band gain of 67.5 dB, a noise figure of 14.5 dB, and a 1-db compression point of −12.39 dBm. Additionally, the BPF consumes a DC power of 1.22 mW and occupies an active area of only 8.85 μm × 10.3 μm.

A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications

AbstractA differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (VDD). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm2. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.

A 4-bit active-inductor-based digitally programmable low noise amplifier (AI-DPLNA) with a tunable and reconfigurable structure

In this paper, a band selective, active-inductor-based digitally programmable low noise amplifier (DPLNA) with a reconfigurable structure is presented. The reconfigurablility of the DPLNA is provided by a programmable current steering network, size-scalable cascode core, and input matching network, which are merged together, and along with a programmable active inductor (AI) as a replacement to huge passive inductors, a compact reconfigurable AI-DPLNA structure is achieved. The size-scalable source degenerated cascode structure is used as the core of the proposed DPLNA, and as a part of current steering network, its output current is reused for biasing the programmable active inductor (AI), which acts as the tank circuit for a narrow-band operation. The operation frequency of DPLNA is controlled by AI load and input matching circuit. A 2-bit programmable current steering network combined with the size-scalable cascode core set the operation frequency of the AI by adjusting its transconductance. Another 2-bits control the AI’s capacitance and also configure the input matching network. Using a TSMC 0.18μm CMOS technology, the simulated 4-bit AI-DPLNA gives a frequency band in the range from 1.816 GHz to 2.631 GHz, an input return loss (LRT) greater than 16.37 dB, a gain (S21) from 11 to 12.57 dB, and a minimum noise figure from 2.6 to 4.2 dB. It consumes a power of 11.4 mW to 12.3 mW from a 2 V supply, and occupies a silicon area of 0.0135 mm2. In addition to PVT and post layout simulations, a prototype of the DPLNA is implemented and tested using through-hole parts to verify the reconfigurability of the proposed structure.

Improved Implementation of Chua’s Circuit on an Active Inductor and Non-Autonomous System

Chua’s circuit is a well-established model for studying chaotic phenomena and is extensively implemented in fields like encrypted communication. However, a traditional Chua’s circuit has large volume, high component precision requirements and limited adjustable parameter range, which are not conducive to application. In order to solve these problems, we propose an improved implementation of Chua’s circuit on an active inductor and non-autonomous system. First, we adopt the strategy of using active inductors instead of traditional passive inductors, achieving the miniaturization of the circuit and improving the accuracy of inductance. In addition, we present the theory of substituting non-autonomous systems for classical autonomous systems to reduce the requirements for the accuracy of components and improve the robustness of the circuit. Lastly, we connect the extension resistor in parallel with Chua’s diode to optimize circuit structure, thereby increasing the range of the adjustable parameter. Based on the three improvements above, experiments have shown that the average maximum error tolerance of components of our improved design has been increased from 1.88% to 7.38% when generating a single vortex, and from 4.73% to 12.61% when generating a double vortex, compared with the traditional Chua’s circuit. The range of the adjustable parameter has been increased by 195.83% and 36.98%, respectively, when generating a single vortex and double vortex. In summary, our improved circuit is more practical than the traditional Chua’s circuit and has good application value.

A Novel Active Inductor Based Low Noise Amplifier for Analog Front End of Bio-medical Applications

A Novel Active Inductor Based Low Noise Amplifier for Analog Front End of Bio-medical Applications

A gyrator-C active inductor based tunable low noise amplifier for sub-GHz frequency range

The propose exhibits a tunable low noise amplifier (LNA), which provides the tunability at sub-GHz frequency range and hence can become choicest frequency range for 5 G applications. Common source (CS) with source degeneration inductor LNA is proposed; in which the inductor in source branch is replaced by gyrator-c active inductor which not only reduced the overall area of the circuit but can also be used to provide the feature of tunability by changing the bias voltage of CMOS based active resistor in feedback branch. Therefore, instead of having a LNA circuit for the fixed frequency, a single tunable LNA design can be used over a range of frequency from 1 GHz to 5 GHz. The proposed approach will provide the direct tuning to the circuit. The forward voltage gain achieved is greater than 10 dB, input matching parameter is less than −10 dB and the output matching parameter is less than −10 dB. The average power dissipated is 0.02 W. The results can be tuned by controlling the feedback voltage of tunable active inductor (Tunable_AI). The tunable results can be achieved up to the bandwidth of 1 GHz.

A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS

This paper presents a 16 Gb/s serial link transceiver implemented in 12-nm FinFET CMOS technology. The equalization scheme incorporates a 3-tap feed-forward equalizer (FFE) in the transmitter, a 5-stage continuous time linear equalizer (CTLE), and a 3-tap decision-feedback equalizer (DFE) in the receiver. The proposed FFE structure offers small step size and flexible configuration. The CTLE's high-frequency boost is augmented by integrating an active inductor. A high-accuracy clock and data recovery (CDR) circuit, featuring a cascaded two-step analog phase interpolator (PI) structure, is developed for data retiming. Occupying a footprint of 0.26 mm × 0.63 mm per lane, the transceiver test chip is packaged in a flip chip ball grid array (FC-BGA) module. Measurement results demonstrate a horizontal eye opening of 38 % at a bit error rate (BER) of 10−12 over a channel with 28 dB loss at 8 GHz. Moreover, the power consumption is 68.85 mW per lane at 16 Gb/s.

A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology

In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.

Design and analysis of a low phase noise, wide tunable CMOS based low power VCO with active inductor

Design and analysis of a low phase noise, wide tunable CMOS based low power VCO with active inductor

Area-Efficient and Wideband Tunable Quadrature Colpitts Oscillator with Active Inductors

This study presents a new wide-tunable, area-efficient and low-phase noise quadrature voltage-controlled oscillator(QVCO). Initially, a modified Colpitts voltage-controlled oscillator (VCO) is proposed in which all transistors are cross-connected in a self-biased scheme to increase negative resistance and facilitate the startup condition. Besides, instead of a passive inductor, a modified tunable active inducer (AI) is used in the proposed Colpitts VCO. Then a new AI-based QVCO is presented by the in-phase anti-phase coupling of two identical Colpitts VCOs. The core VCOs are coupled by the current source transistors of the AI and in this way, no extra coupling devices are used. The proposed AI-based QVCO is designed and simulated in TSMC [Formula: see text] CMOS technology by Cadence. Post-layout simulation results show that the proposed QVCO occupies only [Formula: see text] of chip area, and has a phase noise of −106.6[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset from the 0.7[Formula: see text]GHz oscillation frequency. A wide frequency tuning range (FTR) of 68% (i.e., 0.68–1.4[Formula: see text]GHz) is achieved by adjusting the tuning voltage of the active inductor (AI), and the total power consumption is 7.2[Formula: see text]mW. Coarse and fine frequency tuning of the QVCO is available by changing the emulated inductors and varactors, respectively, that gives [Formula: see text] of 1100 and 34[Formula: see text]MHz/V, respectively.

A High-Precision Flat-Top Pulsed Power Supply Topology Based on SFPFN and Active Coupled Inductor Filter

This study presents a power supply topology capable of generating a large current pulse with a long flat-top duration and a high output voltage. The proposed topology is based on the sequentially fired pulse forming network (SFPFN) and the active coupled inductor filter. The SFPFN generates the primary inaccurate current pulse, and the filter then shapes the current to achieve accurate output. In order to achieve the required accuracy, a novel active coupled inductor filter is proposed which consists of a switched-mode compensator, an auxiliary thyristor pair, a DC bias capacitor, and a coupled inductor. It is designed to deviate most of the voltage and current stress to the coupled inductor, the auxiliary thyristor pair, and the DC bias capacitor, thus reducing the semiconductor devices requirements of the switched-mode compensator. Experimental results based on a 335 A low-power prototype verified the capability of the proposed topology to produce high-precision current pulses and the potential to be generalized to high-power scenarios.

High step up DC–DC converter with low conduction losses and reduced switching losses

AbstractThis article presents a novel high step up converter based on the active switch inductor (ASL) technique for renewable energy source applications. The coupled inductor technique provides an opportunity to increase the gain. The proposed converter exploited the leakage inductors to provide zero current switching (ZCS) turn‐on for both switches. Therefore, there is no need for an auxiliary circuit, which simplifies the structure. Also, all diodes turn off under ZCS, which eliminates the reverse recovery problem and results in reduced switching losses. The energy of the leakage inductor is recycled, and the voltage spike on the switches is limited. In addition, all semiconductor voltage stresses are clamped below the output voltage. Hence, components with lower on‐resistance can be utilized to reduce conduction loss. Because of the reduction in power loss, the efficiency rises to 97.2% at 250 W output power. It also benefits from the current sharing of the interleaved structure. The operating principles, design considerations, and comparison to other topologies are discussed. To verify the effectiveness of the proposed converter, a prototype converter with 250 W of output power, 50 V of input voltage, 500 V of output voltage, and 100 kHz of switching frequency is implemented.

On-Chip Tunable Active Inductor Circuit for Radio Frequency Ics

The work presents a design of a gyrator-based on-chip tunable active inductor (AI) which can become an integral part of high-frequency integrated circuits. The proposed AI uses the Floating gate technology-based PMOS (FGPMOS) simulation model, where the on-chip, non-volatile programming ability of FGPMOS is used as a tunable active feedback resistor. The circuit specifications are first derived for the application at 800MHz to 2GHz. The design is simulated at 350nm CMOS technology and shows a temperature sensitivity of 0.13mV/oC as well as a noise sensitivity of about 10.97nV/Hz. The precise programming range of inductance value from 3nH to 9nH can be achieved. The circuit has a power dissipation of 5.02mV and a moderately high-quality factor of about 120. The layout of the proposed circuit has been designed on Cadence Virtuoso and fabricated at ON-Semiconductor, C5 CMOS process foundry of MOSIS fabrication service, USA. The complete design has a chip area of 18x30µm2. The fabricated results illustrate the on-chip tuning ability of the proposed AI from 3nH to 7nH with the help of externally applied Tunnelling and Injection voltages, respectively. The proposed design also simulates a tunable bandpass filter and a tunable Low Noise Amplifier.

The development of a 10.7-MHz fully balanced current-tunable bandpass filter with Caprio technique

Bandpass filters are integral in modern communication systems for selecting specific frequency ranges to ensure interference-free signal transmission and reception. This paper explores various bandpass filter designs, including those using active inductors, transmission-line unit-cells, microstrip open-loop resonators, and dual-port dual-frequency integration antennas. The focus is on the 10.7-MHz bandpass filter, widely used in FM radio and television systems. The study evaluates current-controlled and balanced designs, analyzing their performance, advantages, and drawbacks. Unique trade-offs in terms of linearity, distortion, temperature sensitivity, and component variations are discussed. Additionally, advancements in filter technology and diverse design options are presented. The paper introduces a novel current-balanced, frequency-adjusted bandpass filter to address odd-order noise issues. This filter aims to achieve high linearity, harmonic distortion attenuation, and the elimination of even-order harmonics. Through synthesis, analysis, simulation, and comparison with traditional filters, the proposed design enhances signal quality and efficiency. The fully-balanced current-tunable bandpass filter with the Caprio technique at 10.7 MHz is developed, exhibiting symmetrical characteristics with lower total harmonic distortion. The circuit’s structure is simple and adaptable for integration, validated through consistent simulation results. The study concludes by emphasizing the constant sensitivity of transistor differential amplifier circuits to the center frequency and the linear relationship between center frequency and adjustable bias current. The suggested transistor and capacitor selection criteria contribute to optimizing the circuit’s performance, aligning with the Caprio technique’s recommendations. Overall, this research presents a promising solution for achieving high-quality signal transmission in contemporary communication systems

A Review on Recently Reported Grounded CMOS Active Inductors

A Review on Recently Reported Grounded CMOS Active Inductors

Performance Analysis of a Reconfigurable Mixer Using Particle Swarm Optimization

In this article, a novel 1.8-5 GHz downconversion mixer is presented. The mixer is designed and simulated using SiGe 8HP 130 nm CMOS process technology. The proposed mixer is implemented by incorporating a double-balanced configuration, active inductor, and current mirror techniques. For performance optimization of the proposed mixer, different algorithms such as the genetic algorithm (GA), inclined plane system optimization (IPO) algorithm, and particle swarm optimization (PSO) algorithm have been used. Compared to existing works, this design shows an enhanced conversion gain (CG), a third-order input intercept point (IIP3), and return loss ( S 11 ) at the expense of the noise figure (NF). Additionally, the design consumes low power and covers a small chip area compared to other state-of-the-art devices. PSO shows the most promising results when compared to other optimization algorithms’ results. According to the measurement results after PSO optimization, the mixer attains a maximum CG of 25 dB, an IIP3 of 4 dBm, and a NF of 5.2 dB at 5 GHz, while consuming only 15 mW of DC power. The mixer operates at 1.2 V and covers 0.8 mm2 die area.