Size Of Active Area Research Articles

Development of high-speed Imaging Plate detector

The Imaging Plate (IP) has the excellent properties of a large active area size and a wide dynamic range, however, the long readout time of the stored image is becoming the greatest drawback at synchrotron radiation facility. To overcome this difficulty, a high-speed IP detector, which can readout a large number of 400×400 mm 2 IPs successively in less than 60 s/IP has been designed and developed for protein crystallography.

An alternative approach to hot spot identification using in situ gamma spectrometry measurements on a grid.

We describe the application of a computer code developed to analyze data from a series of in situ gamma spectrometry measurements on a grid. The code was designed to be used as a tool when evaluating compliance with regulations that set limits on the size and magnitude of elevated activity areas (also known as "hot spots"). It calculates location and magnitude of potential elevated activity areas consistent with the data, and for each potential elevated area it generates a corresponding distribution of radionuclides in the soil. The algorithm uses a maximum entropy deconvolution of the data, followed by further analysis. A test case using data from actual field measurements is presented.

The stability of Si1−xGex strained layers on small-area trench-isolated silicon

The combined effects of isolation stress, active area size, and SiGe misfit strain on dislocation generation in an advanced SiGe heterojunction bipolar transistor (HBT) process were studied. Eight-inch wafers were patterned with polysilicon-filled deep, and oxide-filled shallow trench isolation similar to that used in IBM's analog SiGe HBT technology. Half of the wafers were subjected to an additional stress-producing oxidation prior to SiGe growth. Si1−xGex films containing 0, 5.5, 9, and 13 at.% Ge were grown epitaxially by ultrahigh vacuum chemical vapor deposition (UHV CVD). The films were of constant thickness with an intrinsic Si cap. Some samples received an additional relaxation anneal following deposition. After the growth and anneal cycles, the dislocation density was determined by transmission electron microscopy (TEM). On nonstressed samples, no dislocations were observed in the device areas, even at Ge concentrations which are not stable to misfit dislocation generation in blanket form. This small area effect has been observed on patterned substrates that do not have functional device isolation. On the stressed-isolation wafers, the compressive stress from the oxidation of the trench sidewalls was found to intensify stress in the SiGe films, and to lower the critical strain at which misfit dislocations appeared. In large active areas on these wafers, two distinct dislocation regions were observed. Defects at the edge resembled those caused by isolation stress, while the defects in the center were more typical of the misfit dislocations associated with lattice-mismatch epitaxial films. It is clear that isolation stress must be minimized when fabricating integrated circuits using SiGe epitaxial films. It is also evident that SiGe films grown on nonstressed isolation exhibit the same increase in critical thickness with decreasing lateral dimension that has been observed on much simpler patterned substrates.

Large-aperture germanium detector package for picosecond photon counting in the 05–16-mm range

We report the design, construction, and parameters of a detector package based on a germanium avalanche photodiode operated in the Geiger mode cooled to 77 K. The new design of the active quenching circuit, proper diode structure, and cryogenic cooling setup permitted us to increase the detector's active area to 0.1-mm diameter while maintaining an acceptable dark-count rate, timing resolution, and photon-counting sensitivity at 1.54 microm. The active-area size and the compact design of the detector package permitted its application in satellite laser ranging at 0.532- and 1.543-microm wavelengths, yielding subcentimeter ranging precision.

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

A 286 MHz 64-b floating point multiplier with enhanced CG operation

This paper presents a high speed 64-b floating point (FP) multiplier that has a useful function for computer graphics (CG). The critical path delay is minimized by using high speed logic gates and limiting the stage number of series transmission gates (TGs). The high speed redundant binary architecture is applied to the multiplication of significands. This FP multiplier has a special function of "CG multiplication" that directly multiplies a pixel data by an FP data. This multiplier was fabricated by 0.5-/spl mu/m CMOS technology with triple-level metal of interconnection. The active area size is 4.2/spl times/5.1 mm/sup 2/. The operating cycle time is 3.5 ns at the supply voltage of 3.3 V, which corresponds to the frequency of 286 MHz. Implementation of CG multiplication increases the transistor count only 4%. Also, CG multiplication has no effect on the delay in the critical path.

Optimization of the coupling between a tapered fibre and a p-i-n photodiode

With increasing information flow, direct illumination of the photodiode intrinsic layer from the end of a fibre becomes a necessity. The active area size of the photodiode is much smaller than the spot size in the fibre. This paper proposes an optimized scheme for direct coupling between the fibre and the device. Different fibre extremities are investigated. It is shown that optical coupling could be optimized with an acid-etched taper ended by a lens of 13 mu m diameter or by a pulled and melted fibre with certain conditions of profiles.

Ballistic electron transfer in GaAs submicrometer diodes with Shottky-barriers

As it's well. l~own, the increase of the operati.ng frequencies of GaAs Shcttky barrier diodes was aocompined by decrease of devices active area size up to submicrometres. Application of a microwave signal to the diode with submicrometre active area provides penetrating of a microwave e!ectromag~etic field to the neutral part of the diode active area. It leads, in its t~mn to electron heating and unstationaz~ phenomena taking place d~'ir~ the drift of electrons through neutral area. The <mstationary electron drift influences considerably the boundary character of depletion area moving Lmder the barrier and, as a consequence such diode charcterististics as cut off operating frequency and diode barrier capacity modulation depth. The object of this paper is to investigate theoretically heating and ballistic electron transfere influencir@ the main dynamic parameters of G~s Shottky-barrier diode. The diode active area was devided into a deplation area and the neutral area to simulate the diode operatir~ at high frequencies [I]. Electric field distribution in the diode was determined by Poisson-equation having in a deplation area the view: