Achieve Power Efficiency Research Articles

Topology generation and performance enhancement based on channel assignment optimization for hybrid wireless NoC with large system size

To achieve the efficient topology generation of upper-layer network in hybrid wireless NoC with large system size, a method of topology generation and performance enhancement based on channel assignment optimization is proposed. The method is implemented under certain signal-to-interference plus noise ratio (SINR) and strict resource budget by establishing relevant models of power consumption and interference for hybrid wireless NoC. A communication protocol with low overhead based on weighted conflict graph and two-level wireless token arbitration mechanism is designed for hybrid WiNoC with large system size. The designed protocol could handle channel contention and reduce the waiting time to get access to a wireless channel effectively. It improves obviously the frequency channel utilization. The experimental simulation demonstrates that the resulting topology generated by channel assignment optimization outperforms the conventional counterparts in terms of achievable throughput, power efficiency and latency at the cost of little area overhead.

An Irregular Topology Generation Using Power-Interference Co-Optimization for Hybrid Application-Specific Wireless NoC

Aiming at the efficient topology design of upper-layer network in hybrid application-specific wireless Network-on-Chip (NoC), we propose a new design method of power-interference collaborative optimization (PICO) after analyzing the potential factors of high power consumption and interference, and establishing relevant mathematical model. The design method is used for generating optimal irregular topology of ultralow power-interference using effective wireless link placement and channel assignment based on heuristic search algorithm under certain signal-to-interference plus noise ratio and strict resource constraints, such as the available number of wireless links and silicon area. In addition, the traffic balance between channels is carefully considered in the topology optimization. The theoretical calculation and cycle-accurate simulation results demonstrate that the resulting irregular topology generated by the co-optimization design method outperforms the conventional counterparts in terms of achievable throughput, power efficiency and bandwidth.

Techno-economic assessment of small-scale integrated biomass gasification dual fuel combined cycle power plant

This paper presents theoretical study of the concept of a small-scale combined cycle system composed of natural gas fired microturbine and Organic Rankine Cycle, integrated with thermal gasification of biomass. A conventional natural gas fired microturbine engine is applied within the system. Gaseous fuel from an updraught biomass gasification reactor is burned in duct burners located in the exhaust gas stream downstream of the turbine. Enthalpy of the combustion gases is used in the ORC cycle. The only product of the system is electric energy. Mathematical modelling of the system gives estimated values of achievable power and energy efficiency of the proposed setup. The plant can be considered as a robust technology for utilization of scattered biomass resources located in places where a natural gas network is available. The main issues addressed in the paper are: configuration of the ORC technology and allocation of generated electricity between natural gas and biomass. Energy and exergy allocation keys are demonstrated. An initial cash flow calculations are presented in order to assess financial performance of the plant.

Massive MIMO in Spectrum Sharing Networks: Achievable Rate and Power Efficiency

Massive multiple input multiple output (MIMO) is one of the key technologies for fifth generation and can substantially improve energy and spectrum efficiencies. This paper explores the potential benefits of massive MIMO in spectrum sharing networks. We consider a multiuser MIMO primary network, with N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> -antenna primary base station (PBS) and K single-antenna primary users (PUs), and a multiple-input-single-output secondary network, with N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> -antenna secondary base station and a single-antenna secondary user. Using the proposed model, we derive a tight closed-form expression for the lower bound on the average achievable rate, which is applicable to arbitrary system parameters. By performing large-system analysis, we examine the impact of large number of PBS antennas and large number of PUs on the secondary network. It is shown that, when N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> and K grow large, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> must be proportional to ln K or larger, to enable successful secondary transmission. In addition, we examine the impact of imperfect channel state information on the secondary network. It is shown that the detrimental effect of channel estimation errors is significantly mitigated as N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> grows large.

Magnetic Induction-Based Simultaneous Wireless Information and Power Transfer for Single Information and Multiple Power Receivers

Magnetic induction (MI)-based communication systems have gained increased attention in recent years. Typical applications for these systems lie in the area of wireless power transfer, near-field communication (NFC), and wireless sensor networks in challenging environments. In this paper, a system for simultaneous wireless information and power transfer (SWIPT) using MI-based signal transmission is designed for supporting one data stream and multiple parallel power streams. One of the possible applications for this scheme is an NFC-based access point. The overall system is optimized to guarantee a certain quality-of-service for the data stream as well as a maximum sum receive power for all power receivers (max-sum problem) or a maximum receive power for the worst power receiver (max-min problem), respectively. Both optimization problems turn out to be non-convex, such that the optimum solution cannot be found with limited computational complexity. Hence, we provide efficient suboptimal solutions. In this context, a convex approximation of the transmit power constraint in MI-based multiple-input multiple-output systems turns out to be very useful. A very high achievable power efficiency renders the proposed MI-based SWIPT system very promising.

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.

A Green and Robust Optimization Strategy for Energy Saving Against Traffic Uncertainty

This paper introduces a green and robust optimization scheme based on hose model with bound of link traffic (HLT), in order to achieve power savings in the networks with traffic uncertainty. Most of the studies on green communications nowadays are based on estimates of real traffic matrix. However predicting the traffic matrix is a difficult task for network operators. Further, these models may not be fully applicable in a context where the traffic often fluctuates. By using HLT, the knowledge of the exact traffic information is not required. The traffic is specified by the total outgoing and incoming amount at each node and the total traffic going through each link. We formulate the problem as a mixed integer linear programming (MILP) problem, with an objective to reduce the flow through each link and allow the links to be put to sleep mode. We develop a heuristic to mitigate the limitations of the MILP formulation. Simulation results show that green HLT, while being robust to traffic uncertainty, achieves power efficiency comparable to the models where the knowledge of the traffic information is required.

A high power efficient multi-waveform current stimulator used in implantable neural stimulation

This paper presents a current stimulator circuit that its output can be configured to generate the three most efficient current waveforms used in neural stimulation; rising exponential, falling exponential and rectangular. The stimulation amplitude range can be varied from 0 to 1 mA in a manner that each range can be divided into 16 steps by a 4 bit binary weighted digital to analog converter (DAC). The DAC features the maximum DNL and INL of 0.008 and 0.096 LSB respectively. Rising and falling exponential time constants are tunable from 13 to 106 $$\upmu$$μs. The approach for producing both rising and falling exponential currents is to apply a controllable rising and falling ramp voltage to the gate of the NMOS transistors which are biased to work in the subthreshold region while for the rectangular pulse, a constant subthreshold voltage is needed instead. The ramp generator used in exponential mode, employs a proposed low power 5 nA current source followed by a 3-bit current steering DAC. In the output stage, the stimuli current is buffered through the gain boosting technique which needs the maximum headroom voltage of 0.15 V. The DC output impedance is increased up to at least 24 M$$\Omega$$Ω. A simple electrode shortening is used for the charge balancing purpose at the end of the stimulation phases. The presented stimulator is designed and simulated in a 180nm CMOS technology and for the output driver, a HV 180 nm CMOS is used with the supply voltage equal to 3.3 V. The simulated power consumption of the proposed stimulator for one channel is 23.2 $$\upmu W$$μW and the maximum achieved power efficiency is 94.7 $$\%$$%.

Integrated charge pumps: a generalised method for power efficiency optimisation

Charge pumps (CPs) represent the most common solution for the implementation of fully integrated DC–DC converters. In fact, as opposed to buck/boost DC–DC converters, that need at least an external inductor, charge pump circuits do not require any external component. However, the achievable power efficiency of these circuits is typically significantly lower than power efficiency of buck/boost DC–DC converters. In this study, we develop a general mathematical model of CPs, aiming to provide basic design considerations for power efficiency optimisation. A quality factor for achievable power efficiency is proposed together with guidelines for the design of efficiency-optimised CPs under the constraint of given output voltage and current values.

Power Efficient Hybrid VM Allocation Algorithm

Virtualization technology in Cloud computing has become important technology to reduce power consumption in data centers. Virtual Machine allocation to hosts is the main concept which carried out during Virtual Machine migrations in data centers. Virtual Machine allocation helps to utilize hardware resources of hosts and leads to power efficiency in Data centers. In the past few years, various mechanisms were proposed to apply algorithms to achieve power efficiency. In this paper, we have proposed a genetic algorithm to optimize various parameters i.e. power consumption, response time, SLA violation and VM migrations. Our proposed hybrid algorithm provisions various VMs to hosts in a way that to minimize power consumption, while delivering approved Quality of Service. Results demonstrate that proposed HVMA algorithm helps to minimize power consumption and to optimize various performance parameters during live migrations in various environment conditions.

Maximum Achievable Constrained Power Efficiencies of MPPM-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$L$ &lt;/tex-math&gt;&lt;/inline-formula&gt;QAM Techniques

The maximum achievable power efficiency of a multipulse pulse-position modulation- $\boldsymbol L$ -ary quadrature-amplitude modulation (MPPM- $\boldsymbol L$ QAM) technique under a constraint on its spectral efficiency is obtained. Variations to this technique that include polarization multiplexing and switching are considered as well. A simple characterization to the maximum achievable power efficiency is derived under the above constraint. Our results are compared with that of traditional QAM techniques under same constraints. The results reveal that at spectral efficiency constraints of 1.5, 2.5, and 3.5 bit/sym/pol, the power efficiency of MPPM- $\boldsymbol L$ QAM technique is better than that of traditional QAM technique by $\sim \boldsymbol {3.9}$ , 2.2, and 1.4 dB, respectively.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and $\Delta \Sigma $ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of $-$ 104 dBc/Hz and 1.5 ps $_{\rm rms}$ integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of $-$ 225.8 dB.

A Self-Powered High-Efficiency Rectifier With Automatic Resetting of Transducer Capacitance in Piezoelectric Energy Harvesting Systems

This paper presents a self-powered rectifier for piezoelectric energy harvesting applications, and the key idea of the proposed system is to reset the transducer capacitor at optimal instants to maximize the extracted power. The proposed rectifier consists of two switches and two active diodes. The switches discharge the transducer capacitor at optimal instants two times for every cycle. The active diodes are based on op-amps with a preset dc offset, which reduces the voltage drop and the leakage current and avoids instability. In addition, the controller for the proposed rectifier is simple to reduce the circuit complexity and the power dissipation. The proposed rectifier was designed and fabricated in 0.18-μm CMOS technology. Measured results indicate that it achieves power efficiency of 91.2%, and the amount of power extracted by the proposed rectifier is 3.5 times larger when compared with the conventional rectifiers. The proposed rectifier does not require any off chip components to enable a full chip integration, and the die area of the proposed circuit is 0.08 × 0.20 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS

A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200---400 mV pp signals at date rates of 1.25---5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm2, while the actual driver occupies only 190 μm2. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below ?138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44---1.4 mW/Gbps with external clock and 2.6---4.7 mW/Gbps with clock synthesizer.

A 1024-channel 6 mW/mm2 optical stimulator for in-vitro neuroscience experiments.

Recent optical stimulation technologies allow improved selectivity and have been widely used in neuroscience research. This paper presents an optical stimulator based on high power LEDs. It has 1024 channels and can produce flexible stimulation patterns in each frame, refreshed at above 20 Hz. To increase the light intensity, each LED has an optical package that directs the light into a small angle. To ensure the light of each LED can reach the lens, the LEDs have been specially placed and oriented to the lens. With these efforts, the achieved power efficiency (defined as the mount of LED light power passing through the lens divided by the LED total power consumption) is 5 × 10(-5). In our current prototype, an individual LED unit can source 60 mW electrical power, where the induced irradiance on neural tissues is 6 mW/mm(2) integrating from 460 nm to 480 nm. The light spot is tunable in size from 18 μm to 40 μm with an extra 5-10 μm separation for isolating two adjacent spots. Through both bench-top measurement and finite element simulation, we found the cross channel interference is below 10%. A customized software interface has been developed to control and program the stimulator operation.

Modelling of maximum power efficiency of charge pump circuits

The loss estimation in a switched-capacitor DC–DC converter has caused much controversy because of the uncertainty of the contribution of device parasitics to the power efficiency of a converter. Beginning from a simple equivalent circuit model, a closed-form solution to the maximum achievable power efficiency of a converter in which both the effects of parasitic resistance and capacitance are taken into account is presented. It has been observed that the peak power efficiency of a Dickson charge pump depends mainly on the equivalent parasitic capacitance of a given technology and its operation mode, which is governed by the choices of the coupling capacitance, on-resistance of the switch, as well as the operation frequency of the circuit.

A 2.4 GHz ULP Reconfigurable Asymmetric Transceiver for Single-Chip Wireless Neural Recording IC

This paper presents a 2.4 GHz ultra-low-power (ULP) reconfigurable asymmetric transceiver and demonstrates its application in wireless neural recording. Fabricated in 0.13 μm CMOS technology, the transceiver is optimized for sensor-gateway communications within a star-shaped network, and supports both the sensor and gateway operation modes. Binary phase-shift keying (BPSK) modulation with high data rate (DR) of 1 to 8 Mbps is used in the uplink from sensor to gateway, while on-off keying (OOK) modulation with low DR of 100 kbps is adopted in the downlink. A fully integrated Class-E PA with moderate output power has also been proposed and achieves power efficiency of 53%. To minimize area usage, inductor reuse is adopted between PA and LNA, and eliminates the need of lossy T/R switch in the RF signal path. When used as sensor, the transceiver with frequency locked phase-locked loop (PLL) achieves TX (BPSK) power efficiency of 28% @ 0 dBm output power, and RX (OOK) sensitivity of -80 dBm @ 100 kbps while consuming only 780 μW . When configured as gateway, the transceiver achieves sensitivity levels of -92, -84.5, and -77 dBm for 1, 5, and 8 Mbps BPSK, respectively. The transceiver is integrated with an 8-channel neural recording front-end, and neural signals from a rat are captured to verify the system functionality.

52.4: Highly Efficient Single‐Unit White OLED Device with Emission from Both Singlet and Triplet Excitons

AbstractWe succeeded in developing a single‐unit hybrid organic light‐emitting diode (OLED) device with efficient light emission from both a phosphorescent layer and a fluorescent layer. The single‐unit hybrid OLED achieved power efficiency higher than that of a two‐unit hybrid tandem OLED with a phosphorescent and fluorescent layers.

Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors

Per-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have a single voltage domain for all processor cores. This is because splitting the single voltage domain into per-core voltage domains and powering them with multiple off-chip voltage regulators (VRs) incur a high cost for the platform and package designs. Although using on-chip switching VRs can be an alternative solution, integrating high-quality inductors for VRs with cores has been a technical challenge. In this paper, we propose a cost-effective power delivery technique to support per-core voltage domains. Our technique is based on the observations that: 1) core-to-core (C2C) voltage variations are relatively small for most execution intervals when the voltages/frequencies are optimized to maximize performance under a power constraint and 2) per-core power-gating devices augmented with feedback control circuitry can serve as low-cost VRs that can provide high efficiency in situations like 1). Our experimental results show that processors using our technique can achieve power efficiency as high as those using the per-core on-chip switching VRs at a much lower cost.

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application

A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY that excludes PLL/DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low-swing IO also achieves power efficiency of 0.105 mW/Gbps.