Achieve Fault Tolerance Research Articles

Optimized measurement-free and fault-tolerant quantum error correction for neutral atoms

A major challenge in performing quantum error correction (QEC) is implementing reliable measurements and conditional feed-forward operations. In quantum computing platforms supporting unconditional qubit resets, or a constant supply of fresh qubits, alternative schemes which do not require measurements are possible. In such schemes, the error correction is realized via crafted coherent quantum feedback. We propose implementations of small measurement-free QEC schemes, which are fault tolerant to circuit-level noise. These implementations are guided by several heuristics to achieve fault tolerance: redundant syndrome information is extracted, and additional single-shot flag qubits are used. By carefully designing the circuit, the additional overhead of these measurement-free schemes is moderate compared to their conventional measurement and feed-forward counterparts. We highlight how this alternative approach paves the way towards implementing resource-efficient measurement-free QEC on neutral-atom arrays. Published by the American Physical Society 2024

Quantum Error Correction and Fault-tolerant Quantum Computing

Quantum error correction (QEC), providing systematic ways for protecting qubits from errors, is essential to achieve fault tolerance in building scalable quantum computing systems. QEC has been becoming the major keyword of quantum technology and research over the past few years with several experimental breakthroughs. In this article, I introduce the basic theory of QEC with all relevant concepts, recent experimental achievements, and technological challenges.

Fault-Tolerant Quantum Computation Using Large Spin-Cat Codes

We construct a fault-tolerant quantum error-correcting protocol based on a qubit encoded in a large spin qudit using a spin-cat code, analogous to the continuous-variable cat encoding. With this, we can correct the dominant error sources, namely processes that can be expressed as error operators that are linear or quadratic in the components of angular momentum. Such codes tailored to dominant error sources can exhibit superior thresholds and lower resource overheads when compared to those designed for unstructured noise models. A key component is the gate that preserves the rank of spherical tensor operators. Categorizing the dominant errors as phase and amplitude errors, we demonstrate how phase errors, analogous to phase-flip errors for qubits, can be effectively corrected. Furthermore, we propose a measurement-free error-correction scheme to address amplitude errors without relying on syndrome measurements. Through an in-depth analysis of logical gate errors, we establish that the fault-tolerant threshold for error correction in the spin-cat encoding surpasses that of standard qubit-based encodings. We consider a specific implementation based on neutral-atom quantum computing, with qudits encoded in the nuclear spin of 87Sr, and show how to generate the universal gate set, including the rank-preserving gate, using quantum control and the Rydberg blockade. These findings pave the way for encoding a qubit in a large spin with the potential to achieve fault tolerance, high threshold, and reduced resource overhead in quantum information processing. Published by the American Physical Society 2024

QCA-based fault-tolerant XOR Gate for reliable computing with high thermal stability

The XOR gate is an essential element in the design of digital circuits due to its versatility and usefulness. The design of XOR gate in this paper is based on Quantum-dot Cellular Automata (QCA) 2D planner technology with no line-to-line intersections. The output amplitude is improved by redundant cell-based design, which also helped reliability and fault tolerance outperform. The proposed XOR gate achieves fault tolerance to single-cell addition and missing-cell defects from 68.48% to 95.33%. In addition, the proposed XOR gate is also fault-tolerant against multiple-cell missing defects, as verified from the simulations. Furthermore, high thermal stability makes the circuit reliable for QCA-based digital design applications. The digital design applications such as 4-bit B2G code converter and a 4-bit parity checker are designed from this XOR gate, utilizing 438 and 414 cells, respectively. This demonstrates its effectiveness in designing fault resilient and reliable circuit designs for various applications.

Mechanically induced correlated errors on superconducting qubits with relaxation times exceeding 0.4 ms

Superconducting qubits are among the most advanced candidates for achieving fault-tolerant quantum computing. Despite recent significant advancements in the qubit lifetimes, the origin of the loss mechanism for state-of-the-art qubits is still subject to investigation. Furthermore, the successful implementation of quantum error correction requires negligible correlated errors between qubits. Here, we realize long-lived superconducting transmon qubits that exhibit fluctuating lifetimes, averaging 0.2 ms and exceeding 0.4 ms – corresponding to quality factors above 5 million and 10 million, respectively. We then investigate their dominant error mechanism. By introducing novel time-resolved error measurements that are synchronized with the operation of the pulse tube cooler in a dilution refrigerator, we find that mechanical vibrations from the pulse tube induce nonequilibrium dynamics in highly coherent qubits, leading to their correlated bit-flip errors. Our findings not only deepen our understanding of the qubit error mechanisms but also provide valuable insights into potential error-mitigation strategies for achieving fault tolerance by decoupling superconducting qubits from their mechanical environments.

A Fault-Tolerant Control Method Based on Reconfiguration SPWM Signal for Cascaded Multilevel IGBT-Based Propulsion in Electric Ships

Electric ships have been developed in recent years to reduce greenhouse gas emissions. In this system, inverters are the key equipment for the permanent-magnet synchronous motor (PMSM) drive system. The cascaded insulated-gated bipolar transistor (IGBT)-based H-bridge inverter is one of the most attractive multilevel topologies for modern electric ship applications. Usually, the fault-tolerant control strategy is designed to keep the ship in operation for a certain period. However, the fault-tolerant control strategy with hardware redundancy is expensive and slow in response. In addition, after fault-tolerant control, the ship’s PMSM may experience shock and overheating, and IGBT life is reduced due to uneven switching frequency distribution. Therefore, a stratified reconfiguration carrier disposition Sinusoidal Pulse Width Modulation (SPWM) fault-tolerant control strategy is proposed. The proposed strategy can achieve fault tolerance without any extra hardware. A reconfiguration carrier is applied to improve the fundamental amplitude of inverter output voltage to maintain the operation of the ship’s PMSM. In addition, the available states of faulty H-bridge are fully used to contribute to the output. These can improve the life of IGBTs by reducing and balancing the power loss of each H-bridge. The principles of the proposed strategy are described in detail in this study. Taking a cascaded H-bridge seven-level inverter as an example, simulation and experimental results verify that the proposed strategy, in general, has a potential future application on electric ships.

A Decentralized Voting and Monitoring Flight Control Actuation System for eVTOL Aircraft

The emergence of eVTOL (electrical Vertical Takeoff and Landing) aircraft necessitates the development of safe and efficient systems to meet stringent certification and operational requirements. The primary state-of-the-art technology for flight control actuation in eVTOL aircraft is electro-mechanical actuators (EMAs), which heavily rely on multiple redundancies of critical components to achieve fault tolerance. However, challenges persist in terms of insufficient reliability, immaturity, and a lack of a measurable evaluation method. This research addresses these issues by elucidating the design requirements for EMAs in eVTOL aircraft and proposing a systematic design and evaluation approach for EMA architecture. A key enhancement involves the incorporation of decentralized voting and monitoring (VoDeMo) mechanisms within the Electronic Control Units (ECUs) to improve the overall safety of the EMA. The paper introduces an innovative triple-dual redundant architecture for aircraft control effectors, comprising three dissimilar lanes of ECUs and two similar redundant parallel channels of power electronics and motors. The design is synergistically supported by a comprehensive evaluation that incorporates quantifiable Model-Based Safety Assessment (MBSA), utilizing both physical simulation and logical safety models. Hardware-In-the-Loop (HIL) tests are conducted on a constructed prototype to validate the proposed architecture.

Utilizing Probability Distribution for Selecting Optimal and Minimal Replicas to Achieving Fault Tolerance in a Distributed System

Utilizing Probability Distribution for Selecting Optimal and Minimal Replicas to Achieving Fault Tolerance in a Distributed System

Customizing the minimum number of replicas for achieving fault tolerance in a cloud/grid environment

Networks consist of numerous resources; it is crucial not to overlook fault tolerance and consider it during planning. This is because errors during implementation can result in wasted time and effort, thereby squandering these resources. One solution to address this issue effectively is to implement the task on multiple resources to minimize the occurrence of failed tasks. However, employing an unspecified or fixed number of resources can lead to the depletion of network resources and the overall failure of the network. Replication plays a pivotal role in enhancing data availability in distributed systems. By storing data in multiple locations, users can still access it even if some copies are unavailable due to site failure. Many replication-based algorithms utilize a predetermined number of iterations per function, which may consume excessive network resources, even if the ongoing task does not require such abundant resources. This paper proposes task replication as a viable mechanism for an efficient and fault-tolerant scheduling system. We introduce an algorithm that dynamically selects the optimal and minimal number of replicas based on the network's failure history. This approach aims to minimize the failure rate during task execution.

Efficient and Secure Data Deduplication in Distributed Cloud Storage: A Fault-Tolerant Model Using Active Learning for Big Data Management

As the big data era advances, more and more redundant data are being expressed in various ways. Data deduplication knowledge has never been more important than it is now for lowering redundant data storage and enhancing data quality. Connecting several data tables and identifying distinct entries that point to the same item is typically required, particularly when multi-source data deduplication is involved. Active learning minimises the amount of data that needs to be annotated and trains the classical by choosing the data pieces with the greatest evidence divergence. This approach offers special benefits when handling massive data annotations. Unfortunately, the majority of existing active learning techniques are rarely used for data deduplication jobs and only use classical entity matching. The research effort suggests a model, a distributed cloud storage method that ensures effectiveness, security, and high availability, to close this research gap. By intelligently distributing data subsets among servers, the suggested approach achieves fault tolerance while preserving redundancy for high availability. This suggested model reduces the amount of storage space and upkeep required for the data while eliminating duplicate copies. Additionally, the data is kept in a highly secure and effective manner. The suggested model's efficacy in fault tolerance, cost reduction, batch auditing, and block- and file-level deduplication is demonstrated by the experimental findings. It performs better than current systems thanks to its robust fault tolerance, minimal time complexity, and excellent deduplication capabilities.

Fault- Tolerant DC-DC Converter with Zero Interruption Time Using Capacitor Health Prognosis

A high-end critical electronic system is expected to have hundreds of electronic subsystems, which rely on the Power Management Unit (PMU) to be energized. Having an efficient PMU is crucial and it requires reliable and well-structured voltage buck converters to translate the supplied voltage levels. The buck converters employed in PMU are expected to be fault tolerant and supply uninterrupted power while serving critical subsystems. Active redundant parallel buck converters employed in PMU to achieve fault tolerance increases overhead in terms of area, cost and power dissipation. In this paper, a DC-DC converter is designed for the PMU by combining two legs of buck converters with an effective output of 3.3 V. A simple yet effective technique is proposed to design a fault-tolerant buck DC-DC converter by bypassing a faulty converter leg. The proposed system utilizes an online signal processing-based method for prognostic fault detection. Ripple content in the voltage of the output Aluminum Electrolytic Capacitor (AEC) is monitored and used as a primary health indicator for the primary buck converter leg. Increase in the output ripple due to degradation is used for the prognosis of primary converter failure. The secondary buck converter leg is activated only upon the confirmed prognosis of a faulty primary converter leg to avoid false triggering. The timely prognosis of primary converter failure and activation of secondary converter facilitates uninterrupted power supply. An experimental setup is built and tested in the laboratory. Experimental results indicate a smooth transition from the primary converter leg to the secondary demonstrating an uninterrupted power supply along with the simplicity and effectiveness of the proposed solution

Enhanced Cauchy Matrix Reed-Solomon Codes and Role-Based Cryptographic Data Access for Data Recovery and Security in Cloud Environment

In computer systems ensuring proper authorization is a significant challenge, particularly with the rise of open systems and dispersed platforms like the cloud. Role-Based Access Control (RBAC) has been widely adopted in cloud server applications due to its popularity and versatility. When granting authorization access to data stored in the cloud for collecting evidence against offenders, computer forensic investigations play a crucial role. As cloud service providers may not always be reliable, data confidentiality should be ensured within the system. Additionally, a proper revocation procedure is essential for managing users whose credentials have expired. With the increasing scale and distribution of storage systems, component failures have become more common, making fault tolerance a critical concern. In response to this, a secure data-sharing system has been developed, enabling secure key distribution and data sharing for dynamic groups using role-based access control and AES encryption technology. Data recovery involves storing duplicate data to withstand a certain level of data loss. To secure data across distributed systems, the erasure code method is employed. Erasure coding techniques, such as Reed-Solomon codes, have the potential to significantly reduce data storage costs while maintaining resilience against disk failures. In light of this, there is a growing interest from academia and the corporate world in developing innovative coding techniques for cloud storage systems. The research goal is to create a new coding scheme that enhances the efficiency of Reed-Solomon coding using the sophisticated Cauchy matrix to achieve fault tolerance

Reliability Analysis of Cold-standby Systems with Subsystems Using Conditional Binary Decision Diagrams

<p>Cold-standby systems have been widely used for conditions with limited power, which achieve fault tolerance and high-reliability systems. The cold spare (CSP) gate is a common dynamic gate in the dynamic fault tree (DFT). DFT with CSP gates is typically used to model a cold-standby system for reliability analysis. In general, inputs of the CSP gate are considered to be basic events. However, with the requirement of the current system design, the inputs of the CSP gate may be either basic events or top events of subtrees. Hence, the sequence-dependency among basic events in CSP gates becomes much more complex. However, the early conditional binary decision diagram (CBDD) used for the reliability analysis of spare gates does not consider it well. To address this problem, the conditioning event rep is improved to describe the replacement behavior in CSP gates with subtrees inputs, and the related formulae are derived. Further, a combinatorial method based on the CBDD is demonstrated to evaluate the reliability of cold-standby systems modeled by CSP gates with subtrees inputs. The case study is presented to show the advantage of using our method.</p> <p> </p>

Fault-Tolerant cooperative driving at highway on-ramps considering communication failure

Cooperative driving has great potential to improve traffic safety and efficiency and has been widely discussed in recent years. However, most existing researches only focus on the ideal communication environment and ignore the potential vehicle communication failure, which poses serious safety threats to traffic safety. To fill this research gap, we propose three designing principles for a fault-tolerant cooperative driving model considering communication failure. We let vehicles make real-time decision adjustments according to changes in communication conditions. Fault and non-fault vehicles can execute different decision models in a distributed manner. We test with on-ramps scenarios in simulations. Experiment results demonstrate the promising performance of the proposed model in achieving fault tolerance while reducing the impacts on traffic efficiency.

Universal logic with encoded spin qubits in silicon

Quantum computation features known examples of hardware acceleration for certain problems, but is challenging to realize because of its susceptibility to small errors from noise or imperfect control. The principles of fault tolerance may enable computational acceleration with imperfect hardware, but they place strict requirements on the character and correlation of errors1. For many qubit technologies2–21, some challenges to achieving fault tolerance can be traced to correlated errors arising from the need to control qubits by injecting microwave energy matching qubit resonances. Here we demonstrate an alternative approach to quantum computation that uses energy-degenerate encoded qubit states controlled by nearest-neighbour contact interactions that partially swap the spin states of electrons with those of their neighbours. Calibrated sequences of such partial swaps, implemented using only voltage pulses, allow universal quantum control while bypassing microwave-associated correlated error sources1,22–28. We use an array of six 28Si/SiGe quantum dots, built using a platform that is capable of extending in two dimensions following processes used in conventional microelectronics29. We quantify the operational fidelity of universal control of two encoded qubits using interleaved randomized benchmarking30, finding a fidelity of 96.3% ± 0.7% for encoded controlled NOT operations and 99.3% ± 0.5% for encoded SWAP. The quantum coherence offered by enriched silicon5–9,16,18,20,22,27,29,31–37, the all-electrical and low-crosstalk-control of partial swap operations1,22–28 and the configurable insensitivity of our encoding to certain error sources28,33,34,38 all combine to offer a strong pathway towards scalable fault tolerance and computational advantage.

Novel Design Method in Wireless Charger for SS Topology with Current/Voltage Self-Limitation Function

This study proposes a novel wireless power transfer (WPT) resonance compensation design method based on the SS topology with a self-limitation function that achieves fault tolerance without additional components when the secondary circuit is in a short and open state. Conventionally, WPT compensation topologies have constant current (CC) or constant voltage (CV) output characteristics. The CC and CV characteristics can lead to overvoltage and overcurrent, respectively. Several control systems have been proposed to counter this issue; however, they tend to increase the cost and weight of the system. The proposed topology has a self-limitation function that limits the voltage–ampere output. Here, the wireless charging system was designed after the parameters were obtained using the proposed analysis. The performance of the proposed design was verified by configuring a 400 W experimental prototype and comparing it with the conventional series–series (SS) topology. Experimental results indicated that the system could effectively limit the output voltage and current resulting from open-or short-circuit states.

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

In signal processing and communication systems, digital filters are widely employed. In some circumstances, the reliability of those systems is crucial, necessitating the use of fault tolerant filter implementations. Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters. As technology advances, more complicated systems with several filters become possible. Some of the filters in those complicated systems frequently function in parallel, for example, by applying the same filter to various input signals. Recently, a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given. Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years. The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response (FIR) components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules. Finally, a simple solution of Double modular redundancy (DMR) based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising. This approach is expanded in this short to display how parallel filters can be protected using error correction codes (ECCs) in which each filter is comparable to a bit in a standard ECC. “Advanced error recovery for parallel systems,” the suggested technique, can find and eliminate hidden defects in FIR modules, and also restore the system from multiple failures impacting two FIR modules. From the implementation, Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation. Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.

An Enhanced Fault-Tolerant and Autoreconfigurable BLDC Motor Drive for Electric Vehicle Applications

Semiconductor switching devices are susceptible to open-circuit (OC) and short-circuit (SC) faults, adversely affecting the reliability of power converters. This article proposes a multiple-switch fault-tolerant and autoreconfigurable brushless direct current (BLDC) motor drive configuration, suitable for electric vehicle applications, owing to its enhanced reliability. The proposed power circuit configuration, along with its fault diagnostic algorithm, is capable of achieving fault tolerance against multiple OC and SC faults. The proposed drive configuration is capable of delivering rated power to the BLDC motor even after the development of several faults in the power semiconductor switching devices. In this power converter, additional switching resources, provided to achieve fault tolerance, get connected only after the occurrence of faults. This feature avoids their unnecessary exposure before the occurrence of faults. Furthermore, the proposed topology requires fewer sensors to implement the fault diagnostic algorithm resulting in reduced cost and increased reliability. This article also presents an analysis that assesses the cost-effectiveness of the proposed drive configuration, which reveals that the additional cost to implement the proposed topology is not more than 6% of the total raw material cost of the conventional BLDC motor drive. Simulation and experimental studies validate the concept of the proposed drive configuration.

Fault-Tolerant Cooperative Driving at Signal-Free Intersections

Cooperative driving shows great potential to improve traffic safety and efficiency and has been well discussed in recent years. However, most existing studies focus on ideal traffic environments and ignore potential vehicle failures in traffic systems, which pose significant threats to traffic safety. Therefore, the fault-tolerant capacity of the existing cooperative driving strategies is questionable. To fill this research gap, this paper proposes a fault-tolerant cooperative driving strategy for signal-free intersections by modeling potential vehicle failure types, aiming to keep a good balance between traffic safety and efficiency. Notably, a rule-based fault-tolerant model is constructed to mitigate the threat of potential vehicle failures to traffic safety and efficiency, and to effectively recover the cooperative driving system after vehicle failures occur. Theoretical analysis and simulation results jointly demonstrate the promising performance of the proposed model in achieving fault tolerance and improving traffic efficiency.

Fault Tolerant Hash Join for Distributed Systems

Nowadays, enterprises are inclined to deploy data processing and analytical applications from well-equipped mainframes with highly available hardware components to commodity computers. Commodity machines are less reliable than expensive mainframes. Applications deployed on commodity clusters have to deal with failures that occur frequently. Mostly, these applications perform complex client queries with aggregation and join operations. The longer a query executes, the more it suffers from failures. It causes the entire work has to be re-executed. This paper presents a fault tolerant hash join (FTHJ) algorithm for distributed systems implemented in Apache Ignite. The FTHJ achieves fault tolerance by using a data replication mechanism, materializing intermediate computations. To evaluate FTHJ, we implemented the baseline, unreliable hash join algorithm. Experimental results show that FTHJ takes at least 30% less time to recover and complete join operation when a failure occurs during the execution. This paper describes how we reached a compromise between executing recovery tasks for the least amount of time and using additional resources.