Accurate Compact Model Research Articles

An Accurate Compact Model for On-Chip Vertically Coiled Transformers

An accurate compact model with a physics-based substrate network for on-chip vertically coiled transformers is presented. The metal coils are modeled by a ladder network, which consists of inductors and resistors. The skin and proximity effects are taken into consideration. The capacitive and resistive parasitics between the metal coils and surrounding sidewalls are characterized using R-C networks. A method used to analytically extract the model parameters is proposed. The model renders excellent agreement with the data from both simulation and measurement over the frequency range of 0.1-20 GHz, for a 2:1 vertically coiled transformer manufactured in IBM 90-nm RF-CMOS technology.

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved.

A SPICE model for a phase-change memory cell based on the analytical conductivity model

By way of periphery circuit design of the phase-change memory, it is necessary to present an accurate compact model of a phase-change memory cell for the circuit simulation. Compared with the present model, the model presented in this work includes an analytical conductivity model, which is deduced by means of the carrier transport theory instead of the fitting model based on the measurement. In addition, this model includes an analytical temperature model based on the 1D heat-transfer equation and the phase-transition dynamic model based on the JMA equation to simulate the phase-change process. The above models for phase-change memory are integrated by using Verilog-A language, and results show that this model is able to simulate the I–V characteristics and the programming characteristics accurately.

An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in Sub-30-nm nand Flash Technologies

We propose an accurate compact model of NAND Flash memory, which is fully compatible with a BSIM-4 model. In sub-30-nm NAND Flash, adjacent cells directly affect the channel-edge potential of the selected cell. Due to such direct-channel interference, previous compact models cannot accurately simulate the characteristics of sub-30-nm NAND strings. In this letter, we describe the interference as the threshold voltage variation due to adjacent cells and change the threshold voltage equation of the BSIM-4 model. The equation is semitheoretically derived. Using the proposed model, we simulated several behaviors of 27-nm NAND Flash strings. The results show more than 90% accuracy compared with the silicon measurements.

Development of Compact Thermal–Fluid Models at the Electronic Equipment Level

The introduction of compact thermal models (CTM) into computational fluid dynamics (CFD) codes has significantly reduced computational requirements when representing complex, multilayered, and orthotropic heat generating electronic components in the design of electronic equipment. This study develops a novel procedure for generating compact thermal–fluid models (CTFM) of electronic equipment that are independent over a boundary condition set. This boundary condition set is estimated based on the information received at the preliminary design stages of a product. In this procedure, CFD has been used to generate a detailed model of the electronic equipment. Compact models have been constructed using a network approach, where thermal and pressure-flow characteristics of the system are represented by simplified thermal and fluid paths. Data from CFD solutions are reduced for the compact model and coupled with an optimization of an objective function to minimize discrepancies between detailed and compact solutions. In turn, an accurate prediction tool is created that is a fraction of the computational demand of detailed simulations. A method to successively integrate multiple scales of electronics into an accurate compact model that can predict junction temperatures within 10% of a detailed solution has been demonstrated. It was determined that CTFM nodal temperatures could predict the corresponding area averaged temperatures from the detailed CFD model with acceptable accuracy over the intended boundary condition range. The approach presented has the potential to reduce CFD requirements for multiscale electronic systems and also has the ability to integrate experimental data in the latter product design stages.

Physical and Electrical Performance Limits of High-Speed Si GeC HBTs—Part II: Lateral Scaling

The overall purpose of this paper is the prediction of the ultimate electrical high-frequency performance potential for SiGeC HBTs under the constraints of practical applications. This goal is achieved by utilizing advanced device simulation tools with parameters calibrated to experimental results of most advanced existing technologies. In addition, detailed electrostatic and electrothermal simulations are performed for determining the parasitic capacitances, temperature increase, and safe operating area of aggressively scaled devices. The important figures of merit are then determined from circuit simulation employing an accurate compact model incorporating all relevant physical effects. Based on the vertical profile found in Part I, this paper focuses on achieving a balanced device design by lateral scaling. It is shown that the peak values of ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) around (1, 1.5) THz may be achievable. Such a performance limit provides still significant headroom for further developing existing processes and makes SiGeC HBTs well-suitable for highly integrated millimeter-wave applications operating within the low-end of the terahertz gap.

Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices

High-voltage (HV) metal-oxide-semiconductor field-effect transistors (MOSFETs) of the laterally diffused metal-oxide-semiconductor (LDMOS) type enable applications over a wide range of bias voltages by optimizing the combined structure of MOSFET and drift region at its drain side. We report a physically accurate compact resistor model of the LDMOS drift region, adapted to the special requirements of the combined structure with a MOSFET. In particular, the reported resistor model captures the effects of the 2-D current flow in the drift region with its complicated bias dependence. The resistor model considers two device-structure-dependent potentials, namely, the internal node potential within the highly resistive drift region and the potential underneath the gate overlap region. The consistent potential-based description over the complete LDMOS device is the key modeling technology for enabling the accurate reproduction of the bias-dependent 2-D current flow and the resulting <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics for a wide range of structure variations with a small number of only six fitting parameters. The reported quasi-2-D resistor model is implemented in the second-generation Hiroshima-university STARC IGFET Model-High Voltage (HiSIM-HV) compact models for HV MOSFETs and is expected to be useful for both, optimization of LDMOS circuits and devices.

An accurate compact model for CMOS cross-shaped Hall effect sensors

The paper describes a new design-oriented compact model for horizontal Hall effect devices. This model is based on the physics of semi-conductor and is simplified according to some assumptions verified through experimental results and/or numerical simulations. Compared to existing models, it has the advantage to take most of the first-order effects into account while allowing fast simulations. A procedure to extract the parameters of the model is given and simulation results are compared to experimental data measured on a cross-shaped sensor designed in a standard 0.35 μm CMOS technology. The maximum error between simulation results and experimental data is less than 1%.

A physically based, accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal-oxide-semiconductor field-effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal-oxide-semiconductor field-effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi-bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self-consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high-κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.

Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction

Abstract This paper presents an effective statistical compact modelling strategy that can precisely capture a statistical set of MOSFET characteristics into industrial strength statistical compact models. 3D simulation of large statistical sample of microscopically different devices is required for statistical compact model extraction when studying the impact of variability in next CMOS technology generations on circuit and system design. For a particular nominal device design the statistical 3D physical simulations needs two orders of magnitude more CPU time compared to conventional TCAD simulations. A data sampling strategy is presented to reduce the number of bias points in simulated device characteristics used as extraction targets for statistical compact model parameter extraction. We show that for a well balanced set of statistical compact model parameters carefully chosen small number of strategic bias points in the simulated I–V characteristics of each microscopically different transistor is sufficient to capture accurately the statistical device behaviour. The corresponding increase in the RMS error is below 1% compared to results from comprehensive bias point set. The impact of the slight reduction of the compact model accuracy on the accuracy of statistical circuit simulation has also been investigated.

High frequency and noise model of gate-all-around metal-oxide-semiconductor field-effect transistors

The surrounding gate (SGT) metal-oxide-semiconductor field-effect transistor is one of the most promising candidates for the downscaling of complementary metal-oxide-semiconductor technology toward the sub-50-nm channel length range since the SGT architecture allows excellent control of the channel charge in the silicon film, thus reducing short channel effects. However, at these dimensions, quantum effects must be considered in order to develop accurate compact models useful for circuit simulations. In this paper we study the influence of quantum effects on dc, radio frequency (rf), and microwave noise for nanoscale SGT transistors including nonstationary effects. We present an analytical charge model for adjusting the charge control computed from the self-consistent solution of the two-dimensional Schrödinger and Poisson equations. rf and noise performances are calculated using the active transmission line method. We compared, on the one hand, classical and quantum charge control models and, on the other, drift-diffusion and hydrodynamic transport models.

A compact quantum model for fin-shaped field effect transistors valid from dc to high frequency and noise simulations

Fin-shaped field effect transistors (FinFETs) are considered to be a very attractive option to improve the performance of complementary metal-oxide-semiconductor devices into the sub-50-nm gate length regime. However, for those dimensions, quantum effects must be considered in order to develop accurate compact models useful for circuit simulations. In this paper, we study the influence of the quantum effects on dc, Radio frequency (rf), and microwave noise for nanoscale FinFET transistors including nonstationary effects. We present an analytical charge model to adjust the charge control computed from the self-consistent solution of the two-dimensional Schrödinger and Poisson equations. rf and noise performances are calculated using the active transmission line method. Comparison between classical and quantum charge control and between drift-diffusion and hydrodynamic models is carried out.

On gate leakage current partition for MOSFET compact model

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.

Evolving Compact and Interpretable Takagi–Sugeno Fuzzy Models With a New Encoding Scheme

Developing Takagi-Sugeno fuzzy models by evolutionary algorithms mainly requires three factors: an encoding scheme, an evaluation method, and appropriate evolutionary operations. At the same time, these three factors should be designed so that they can consider three important aspects of fuzzy modeling: modeling accuracy, compactness, and interpretability. This paper proposes a new evolutionary algorithm that fulfills such requirements and solves fuzzy modeling problems. Two major ideas proposed in this paper lie in a new encoding scheme and a new fitness function, respectively. The proposed encoding scheme consists of three chromosomes, one of which uses unique chained possibilistic representation of rule structure. The proposed encoding scheme can achieve simultaneous optimization of parameters of antecedent membership functions and rule structures with the new fitness function developed in this paper. The proposed fitness function consists of five functions that consider three evaluation criteria in fuzzy modeling problems. The proposed fitness function guides evolutionary search direction so that the proposed algorithm can find more accurate compact fuzzy models with interpretable antecedent membership functions. Several evolutionary operators that are appropriate for the proposed encoding scheme are carefully designed. Simulation results on three modeling problems show that the proposed encoding scheme and the proposed fitness functions are effective in finding accurate, compact, and interpretable Takagi-Sugeno fuzzy models. From the simulation results, it is shown that the proposed algorithm can successfully find fuzzy models that approximate the given unknown function accurately with a compact number of fuzzy rules and membership functions. At the same time, the fuzzy models use interpretable antecedent membership functions, which are helpful in understanding the underlying behavior of the obtained fuzzy models.

Extraction of Accurate Thermal Compact Models for Fast Electro-Thermal Simulation of IGBT Modules in Hybrid Electric Vehicles

An optimized thermal management is of paramount importance when developing efficient and reliable converters for automotive applications. In this paper, we present a new approach to extract accurate compact models for fast electro-thermal simulations of IGBT modules used in hybrid electric vehicles. It is shown that the proposed methodology brings advantages in terms of increased reliability, reduction of the costs, and shortening of the design cycle.

Compact Model Generation for On-Chip Transmission Lines

An approach for the fast and accurate generation of compact distributed circuit models for on-chip transmission lines on lossy silicon substrates is presented. Using a novel ABCD matrix partitioning procedure, accurate distributed circuit models are extracted from scattering parameters obtained from measurements and calibrated full-wave electromagnetic simulations for a small set of transmission-line geometries spanning ranges of design parameter values. A feedforward artificial neural network is trained using the extracted results, and applied to generate accurate compact models for arbitrary values within the bounds of the training ranges. Consequently, the model generation time is greatly reduced compared to conventional approaches by exploiting the interpolation capabilities of the neural network. The compact model generator is fully compatible with HSPICE and SPECTRE-RF and is easily incorporated into parasitic-aware RF circuit design and optimization tools.

Impact of geometrical scaling on low-frequency noise in SiGe HBTs

The influence of geometrical scaling on low-frequency noise in SiGe HBTs is presented. Small-size transistors show a strong variation in noise across many samples, whereas the noise in larger devices is more statistically reproducible. This size-dependent variation in noise can produce challenges for accurate compact modeling. This effect is investigated using reverse-bias emitter-base stress and calculations based on the superposition of generation/recombination noise.

Design, Optimization of RF Spiral Inductors Using Scalable Compact and Accurate Models

This paper presents a practical and structured approach to the design and optimization of RF spiral inductors. The accuracy of proposed modified accurate distributed and scalable compact lumped models are quantitatively compared with experimental results. Based on the new scalable compact lumped model, a quality factor optimization engine is verified. The inductors under study include single/double layer inductors, metallization shunted as well as octagonal shaped inductors. Experimental results suggest that the new modified accurate distributed model is more accurate than existing models for predicting spiral inductor performance to even beyond resonance frequencies. In addition, using a self developed optimization engine, the new scalable compact model is sufficiently accurate in determining the optimum inductor geometry. Consequently, a web-based program (SISOP) is developed to provide RF designers total solution to spiral inductor design, optimization and integration of spiral inductor model into their lump circuit simulators.

An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness

As the gate oxide thickness is vigorously scaled down, quantization-induced charge layer thickness in MOSFETs has to be considered for accurate MOSFET intrinsic capacitance modeling for circuit simulation. We report in this paper an analytical MOSFET intrinsic capacitance model incorporating the concept of charge layer thickness, which was developed based on the self-consistent solution of the Schrodinger and Poisson equations with Fermi-Dirac statistics. The results demonstrate that this model has excellent accuracy and simulation performance.

A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFETs using one single device

A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived.