Accelerated Thermal Cycling Test Research Articles

Reliability and failure modelling of microelectronic packages based on ultrasonic nondestructive evaluation data

Reliability testing and failure modelling is crucial and very challenging for modern electronics, especially safety critical electronics-based systems working under harsh environmental conditions. In this paper, an approach based on ultrasonic Non-Destructive Evaluation (NDE) is proposed to establish a failure model for solder joints which is urgently needed for prognostic and health management of electronics. Printed Circuit Boards (PCB) containing flip-chip and Area Array packages were designed and aged using Accelerated Thermal Cycling (ATC) testing. During ATC testing solder joint degradation was regularly monitored by taking out the test boards from the temperature chamber at four thermal cycle intervals for ultrasonic micro-imaging. Data pre-processing techniques including dynamic range-based intensity normalization, gain compensation, and calibration for random transducer defocusing errors were developed to enhance the data consistency, integrity and accuracy. Furthermore, solder joint image labelling and segmentation methods were developed by exploiting the geometrical features of the solder joints to extract individual solder joints and Region of Interests (ROIs) from the sequential ultrasound images collected throughout the testing. The mean intensity of the ROIs was used as the precursor to degradation to build the solder joint failure model, from which cycles to failure for individual solder joints are finally derived for life prediction.

Predicting Wafer-Level Package Reliability Life Using Mixed Supervised and Unsupervised Machine Learning Algorithms.

With the increasing demand for electronic products, the electronic package gradually developed toward miniaturization and high density. The most significant advantage of the Wafer-Level Package (WLP) is that it can effectively reduce the volume and footprint area of the package. An important issue in the design of WLP is how to quickly and accurately predict the reliability life under the accelerated thermal cycling test (ATCT). If the simulation approach is not adopted, it usually takes several ACTCs to design a WLP, and each ACTC will take several months to get the reliability life results, which increases development time considerably. However, simulation results may differ depending on the designer’s domain knowledge, ability, and experience. This shortcoming can be overcome with artificial intelligence (AI). In this study, finite element analysis (FEA) is combined with machine learning algorithms, e.g., Kernel Ridge Regression (KRR), to create an AI model for predicting the reliability life of electronic packaging. Kernel Ridge Regression (KRR) combined with the K-means cluster algorithm provides a highly accurate and efficient way to obtain AI models for large-scale data sets.

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging.

Several design parameters affect the reliability of wafer-level type advanced packaging, such as upper and lower pad sizes, solder volume, buffer layer thickness, and chip thickness, etc. Conventionally, the accelerated thermal cycling test (ATCT) is used to evaluate the reliability life of electronic packaging; however, optimizing the design parameters through ATCT is time-consuming and expensive, reducing the number of experiments becomes a critical issue. In recent years, many researchers have adopted the finite-element-based design-on-simulation (DoS) technology for the reliability assessment of electronic packaging. DoS technology can effectively shorten the design cycle, reduce costs, and effectively optimize the packaging structure. However, the simulation analysis results are highly dependent on the individual researcher and are usually inconsistent between them. Artificial intelligence (AI) can help researchers avoid the shortcomings of the human factor. This study demonstrates AI-assisted DoS technology by combining artificial intelligence and simulation technologies to predict wafer level package (WLP) reliability. In order to ensure reliability prediction accuracy, the simulation procedure was validated by several experiments prior to creating a large AI training database. This research studies several machine learning models, including artificial neural network (ANN), recurrent neural network (RNN), support vector regression (SVR), kernel ridge regression (KRR), K-nearest neighbor (KNN), and random forest (RF). These models are evaluated in this study based on prediction accuracy and CPU time consumption.

Design guideline on board-level thermomechanical reliability of 2.5D package

A vast range of electronics products have utilized 2.5D packages for better performance and miniaturization. As multi-level assembly technologies are getting mature, 2.5D packaging technology becomes affordable. In this work, design guideline for board-level reliability of a 2.5D package was provided with respect to accelerated thermal cycling (ATC) and power cycling (PC). Finite element models were built and validated step-by-step by warpage measurement. Solder fatigue life in power cycling was investigated with temperature mapping technique merged into the process of scripting, which conducts load transfers from computational fluid dynamics (CFD) simulation to finite element analysis (FEA). ATC test was conducted with solder joint failure analysis. Fatigue life projection model was determined by correlation between tested life data and simulation results. Parametric studies regarding geometry factors and material properties were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. It is found that CTE mismatch between the substrate and the PCB is the major factor affecting board-level reliability in accelerated thermal cycling. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. Designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.

Empirical Solutions and Reliability Assessment of Thermal Induced Creep Failure for Wafer Level Packaging

The accelerated thermal cycling test (ATCT) is a method of testing the electronic packaging reliability characteristic. A component must pass this test before being launched into the market. According to many studies, under thermal loading, the excessive thermal strain and stress occur between the package and substrate because of the coefficient of thermal expansion mismatch, which damages the solder bump of electrical packaging. In the ATCT, −40° C to 125° C is the regular thermal range of packages tested. Furthermore, the homologous temperature exceeds one-third of the melting point (K) of solder, and one should consider the accumulation of creep strain and estimate the creep behavior during the loading procedure; however, the creep strain is very sensitive to mesh size in finite element simulation. Obtaining a stable and reliable creep stain for different packaging structures becomes a must for solder joint reliability assessment. In this paper, we study a feasible and fixed element size, which should be chosen carefully for the same type of electronic packaging structure, for example, wafer level packaging (WLP), as it can affect simulation results and cause the prediction of the packaging life cycle to deviate. In ATCT simulation, there is a big difference in reliability estimation for different element mesh size selection, even if all material properties and structures remain the same. It is essential to find an appropriate and fixed element size for packaging reliability prediction to yield precise and reliable simulation results. This paper aims to find an appropriate element mesh size that can consistently predict the reliability life of various WLPs in an accurate range, and the reliability results of different WLPs under the thermal cycling loading have been validated by experiments. Moreover, the simulation results are summarized by using the Anand and hyperbolic sine creep models with suitable empirical reliability assessment equations, and the results show both creep models can predict the reliability life of WLPs in an accurate range with appropriate mesh control.

Characterization on acceleration-factor equation for packaging-solder joint reliability

The well-known Norris-Landzberg acceleration factor (N-L AF) empirical equation was developed based on the accelerated thermal cycling (ATC) test. It has been widely used for many years to predict product lifetimes. However, some recent test results have shown the insufficiency of this equation when the ramp rates change. The AF equation predicts a longer lifetime when the ramp rate is higher, which contradicts the experimental test data. The reason for this discrepancy is that the N-L AF equation combines both ramp rate and dwell time factors in one frequency term. Thus, modifying the current AF equation to more precisely predict product lifetimes has become an important topic.This study proposes a new AF equation to decouple the effects of the ramp rate and dwell time during an ATC test, replacing the frequency term used in the N-L equation with two new terms. One is related to the ramp rate for the strain rate effect, and the other is related to the dwell time for the creep effect of the packaging solder joint material. The new AF equation produces a good correlation between the simulation and test results for different package types discussed in the literature with various ramp rates and dwell times.

Reliability Assessment of Packaging Solder Joints Under Different Thermal Cycle Loading Rates

In assessing the solder joint reliability using an accelerated thermal cycling (ATC) test methodology, which is widely used in the microelectronics industry, a common type of solder joint failure is the formation of fatigue cracks at the interface between the solder joints and the components. However, ATC tests are quite time-consuming and can take more than a month to complete. Hence, its efficiency has become an important issue. The parameters of the ATC test, such as temperature ramp rate and dwell time, significantly influence fatigue failure in solder joints. Fast temperature cycles can reduce the testing time, but the effects of ramp rate cause variations in solder joints' material properties and mechanics behavior due to strain rates and stress changes. Commonly used lead-free materials with high homologous temperatures induce creep-related solder joint failures. This paper used a temperature-dependent Young's modulus and Garofalo-Arrhenius creep equation to describe the solder deformation response. An energy-density-based empirical equation was used, along with the optimized mesh size in a finite-element model calculation with different solder joint geometries and packaging types such as power modules, and wafer-level chip-scale packages to determine how to accommodate the strain rate effect given various ramp rates.

Board level reliability analysis of chip resistor assemblies under thermal cycling: A comparison study between SnPb and SnAgCu

Accelerated thermal cycling (ATC) tests are conducted for various chip resistor assemblies using the lead-based (SnPb) and lead-free (SnAgCu) solders. The corresponding life prediction models are developed by employing the well-established energy density approach. The life prediction model constants are obtained from the ATC test data. The models are utilized to predict the lifetimes of chip resistor assemblies under a mobile device field condition. The analysis indicates that the lead-free solder used in the chip resistor assembly would offer a longer lifetime under a field condition compared to the lead-based solder regardless of chip resistor types even when a reverse trend is observed in the ATC test results.

Interconnect Reliability Characterization of a High-Density 3-D Chip-on-Chip Interconnect Technology

This paper investigates the solder interconnect reliability of a high-density 3-D chip-on-chip technology under an accelerated thermal cycling (ATC) test condition through finite element (FE) modeling and experimental validation. The fabrication of the 3-D chip-on-chip technology is accomplished with a two-step gap control bonding process to minimize the solder squeezing phenomenon. The alternative goal of this paper is placed on the influences of underfill on the interconnect failure mechanism and reliability. With the calculated plastic strain, the thermal fatigue life of the most critical solder interconnect can be estimated through an empirical Coffin-Manson fatigue life prediction model. The effectiveness of the proposed FE modeling is demonstrated through ATC tests. Finally, to identify the parameters most affecting the lead-free solder interconnect reliability, both parametric FE analysis and a simulation-based experimental design scheme based on a response surface methodology are carried out with the validated FE model. Both the numerical and experimental results that underfill can not only change the interconnect failure mechanism from an interfacial crack between the Al pad and the copper (Cu) layer of the under bump metallurgy to a cohesive solder failure, but also greatly improve the solder interconnect thermal fatigue life by as much as 2.5 times. Furthermore, the experimental design demonstrates that both the Young's modulus of intermetallic compound and thermal expansion coefficient of underfill are identified as the parameters most affecting the solder interconnect reliability of the 3-D chip-on-chip technology.

Accelerated Thermal Cycling Test of Microencapsulated Paraffin Wax/Polyaniline Made by Simple Preparation Method for Solar Thermal Energy Storage.

Microencapsulated paraffin wax/polyaniline was prepared using a simple in situ polymerization technique, and its performance characteristics were investigated. Weight losses of samples were determined by Thermal Gravimetry Analysis (TGA). The microencapsulated samples with 23% and 49% paraffin showed less decomposition after 330 °C than with higher percentage of paraffin. These samples were then subjected to a thermal cycling test. Thermal properties of microencapsulated paraffin wax were evaluated by Differential Scanning Calorimeter (DSC). Structure stability and compatibility of core and coating materials were also tested by Fourier transform infrared spectrophotometer (FTIR), and the surface morphology of the samples are shown by Field Emission Scanning Electron Microscopy (FESEM). It has been found that the microencapsulated paraffin waxes show little change in the latent heat of fusion and melting temperature after one thousand thermal recycles. Besides, the chemical characteristics and structural profile remained constant after one thousand thermal cycling tests. Therefore, microencapsulated paraffin wax/polyaniline is a stable material that can be used for thermal energy storage systems.

Effects of Board Design Variations on the Reliability of Lead-Free Solder Joints

Sn-Ag-Cu (SAC) solder alloys, such as Sn-3.0Ag-0.5 Cu (SAC305) are the popular choices of lead-free solders replacing SnPb solders. However, SAC solders are more brittle in nature due to stiffness and excessive intermetallic compounds growth at the solder joint to pad interface. This leads to higher risk of solder joints failures. Memory module-type smaller lead-free ball grid array (BGA) packages are constantly under dynamic stresses during handling and thermal stresses during operations. It is important to understand the dynamic performance and long-term reliability of memory module lead-free BGAs. It is believed that the printed circuit board (PCB) design variations cause dynamic and long-term failure discrepancies in the fields. In this paper, different pad and trace designs are introduced to evaluate the effects of PCB design variations on the bend and accelerated thermal cycling (ATC) performance of lead-free solder joints. Pad designs with nonsolder mask defined, solder mask defined (SMD), and a unique web design are assembled and tested. Different solder alloys, including SAC305, Sn-1.0Ag-0.5Cu (SAC105) SAC105, and SnPb solders, have been evaluated in this paper. Different PCB materials have also been evaluated in the test. Four-point monotonic bend tests are performed to characterize the bending performance variations with different PCB designs and compared with conventional Sn-Pb solder. The SMD pad is shown to have the best bend performance among all other types of designs in this paper. In addition, this design also shows improvement in mitigation of PCB pad cratering with lead-free solders. Wide trace width seems to degrade the strength and is not preferred. Just as it shows superior shock resistance when compared with SAC305, the SAC105 solder alloy also shows better bend performance. There is no significant improvement in bend performance with web design. After aging treatment, bend performance of both SAC305 and SAC105 degraded by up to 34% and 29%, respectively. However, the bend performance of eutectic SnPb is actually improved after aging. ATC tests are performed to investigate the effects of design variations on the long-term reliability of lead-free solder joints; SMD design shows less reliability life than others. The implications of these results for the reliability of lead-free solder joints are discussed in this paper.

Effects of Multiple Reworks on the Accelerated Thermal Cycling and Shock Performance of Lead-Free BGA Assemblies

In this paper, the effect of multiple rework cycles (up to 5×) on reliability of lead-free assemblies is investigated. The test vehicle is designed to capture the reliability impact of rework processes on interconnects of ball grid array (BGA) devices, the solder joints of its adjacent components, and BGA devices of clamshelled devices. The effects on high aspect ratio plated through hole (PTH) vias and microvias are also considered. A variety of BGA packages, such as flip-chip BGA, plastic BGA, and chip array BGA are selected to represent different package technologies and stress levels. The effect of multiple reworks on the behavior of lead-free solder joints during accelerated thermal cycling (ATC) and mechanical shock is extensively explored in this paper. The experimental and analytical findings showed that multiple reworks significantly degraded the ATC performance of the reworked assemblies by up to 50% in terms of characteristic life. It is also found that multiple reworks affect the PTH vias significantly. The combination of increased lead-free rework temperature excursions and high-end printed circuit board (PCB) aspect ratios may incur higher stresses in the PTH copper barrel. Early failures are observed post multiple reworks and the subsequent ATC test due to PTH barrel cracking. However, the effects of multiple reworks are less severe for devices with microvias compared to those with PTH vias. Multiple reworks also cause severe degradation of long-term performance of devices with clamshell designs. With proper control in rework process, multiple reworks have minimum effects on the adjacent BGA solder joints. In addition, failure analysis is performed in order to study the impact of multiple rework on the microstructure of SnAgCu solder joints. It is found that the intermetallic compounds (IMC) layer grows thicker as the number of reworks increases; however, the IMC growth rate and morphology are dependent on the surface finish of the package substrate. The failure mode and failure mechanism after ATC are also compared for different number of rework cycles. The implications of these results for the reliability of lead-free solder joints are discussed in this paper.

Reliability of Lead-Free Solder Joints Under a Wide Range of Thermal Cycling Conditions

In this paper, we report a comprehensive set of accelerated thermal cycling (ATC) tests that were performed on test vehicles with different package types, sizes, pitches, and solder joint alloy metallurgies using four different thermal cycling profiles: 0 to 100, -40 to 125, -55 to 125, and -60 to 150°C. Samples from the tests were analyzed for their failure modes, and failure rates were calculated by using Weibull statistics. The characterized life for each test condition was determined and analyzed. The impact of solder alloy metallurgies, package types, sizes, and pitches on acceleration factors of the ATC tests to fatigue life was also analyzed and discussed. The quantified discrepancies among several acceleration factors from different studies compared to the experimental data presented in this paper are illustrated. The results provide valuable guidance on the effects of package types, size, pitches, and solder joints alloy metallurgies on various ATC test conditions. In addition, failure analysis was performed at different stages of the tests for each thermal cycling condition. Dramatic failure mode shifts at extreme ATC conditions were observed. The significance and the long-term impact of the failure modes and failure mechanism shift between various ATC test conditions to the life prediction of lead-free solders are extensively discussed.

Laser moiré interferometry for fatigue life prediction of lead-free solders

A laser moiré interferometry based technique to predict the fatigue life of Sn4.0Ag0.5Cu solder joints in a plastic ball grid array (PBGA) package when subjected to a typical accelerated thermal cycling (ATC) loading has been presented in this paper. The fatigue life is estimated by measuring the in-plane strains in the solder joints at various temperatures. The methodology can be used to predict the reliability of the package in a matter of few days as opposed to many months taken by an actual ATC test. The technique can be extended to include multiple temperature regimes in a single experimental setup thereby making it possible to estimate the fatigue life of solder joints when subjected to various ATC loading profiles in a very short duration.

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques. This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound-interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated. Accelerated thermal cycling (ATC) tests were performed in two phases on flip chip package (FCP) test vehicles with 63Sn37Pb solder bumps. In phase I, four boards were thermal cycled up to 70 cycles. Every ten cycles, the boards were taken out of the chamber and FCPs on each board were tested for detecting presence of cracks using resistance and laser ultrasound testing methods. These measurements were repeated every 10 cycles and stopped after 70 cycles. Laser ultrasound testing results show that starting from 10 cycles, testing values began to increase gradually until 50 cycles when there was a sharp jump (through crack verified at 50 cycles with cross section). Cross section was done only after 70 cycles, and the results show that solder bumps at the corners had through cracks, while solder bumps at the center had partial cracks. Phase II study was a refinement of phase I study. In phase II study, seven boards were thermal cycled starting from 27 cycles to 56 cycles at an increment of approximate five cycles. After every five cycles, only one board was pulled out and tested in order to track crack initialization and propagation in solder bumps. Smaller thermal cycle increments were used in phase II to help determine when cracks initiated and propagated. It was shown that laser ultrasound technique could nondestructively track solder bump crack propagation due to thermal fatigue. The Anand's viscoplastic constitutive model was used in FE simulation to describe the inelastic deformation behavior of solder bumps in thermal cycling. A 3-D FE model was implemented using ANSYS on the same FCP as used in the ATC testing. The stress-strain results were extracted from FE modeling and the inelastic strain energy density (SED) increment per cycle calculated from the critical solder bump was used as a failure parameter. In this paper, it was demonstrated that there is a good correlation between the inelastic SED increment extracted from FE simulation and experimental results from nondestructive laser ultrasound testing.

IMC Growth Mechanisms of SAC305 Lead-Free Solder on Different Surface Finishes and Their Effects on Solder Joint Reliability of FCBGA Packages

Intermetallic compound (IMC) growth behavior of lead-free solder plays an important role in ball grid array (BGA) solder joint reliability for flip chip BGA (FCBGA) packaging applications. The growth mechanism of IMC is reported based on a diffusion model. Thermal treatment such as accelerated thermal cycling (ATC) and isothermal aging exposure also contribute to the growth rate and morphology of lead-free solder IMC. Among the lead-free solder alloys, Sn-3.0wt.%Ag-0.5wt.%Cu (SAC305) solder is a promising substitute for Sn-Pb because of its good mechanical properties and wettability with current surface finishes. After thermal exposure, BGA solder joint reliability is degraded due to IMC formation and growth. In this study, two different thermal treatments, ATC and isothermal aging, and two different pad surface finishes, solder on pad (SOP) and electroless Ni immersion gold (ENIG), are considered in terms of IMC growth rate and mechanical solder joint reliability. An SOP finished interface forms a thin ε-phase Cu3Sn layer and a scallop-like η-phase Cu6Sn5 layer. In contrast, the ENIG finished interface forms a thick (Cu,Ni)6Sn5 IMC layer and prevents overall IMC growth. Different surface finished test vehicles are evaluated in an ATC test in a 0°C to 100°C temperature range and the Ni diffusion layer shows a longer solder joint fatigue lifetime than the nondiffusion barrier interface based on the micro cross-section and dye penetration analysis results. In an isothermal aging test at 100°C and 150°C, the aging temperature and time are valid factors to decide mechanical shock reliability. Interfacial fractures are found in the 100°C aged test vehicle due to easier crack propagation at the interface between the thin Cu3Sn layer and the scallop-like Cu6Sn5 layer based on SEM microstructure analysis results. Finally, this investigation proposes how to improve solder joint reliability and prevent interfacial fracture for SAC305 lead-free application.

Microstructure evolution based acceleration factor determination for SnAgCu solder joints during thermal cycling

The reliability of lead-free solder used in electronic packages during field-use conditions has traditionally been determined using accelerated thermal cycling (ATC) combined with a Norris-Landzberg type acceleration factor. Limited amount of work exists in quantifying the microstructure evolution of lead-free solder during thermal cycling especially during long-term thermal excursions. A phase coarsening based microstructure evolution has been used in the present work to determine the acceleration factor during thermal cycling. Two different plastic ball grid array (PBGA) packages with different sizes and two different lead-free solder alloys, Sn4.0Ag0.5Cu and Sn3.0Ag0.5Cu, were chosen for the study. The acceleration factor can be determined and hence the package can be qualified for field-use conditions in about the same time duration it takes to perform the ATC test.

Torsion test applied for reballing and solder paste volume evaluation

Electronic second level interconnect reliability characterization by accelerated thermal-cycling (ATC) test for long-term mission profile is costly and high time consuming. In order to reduce test duration, the torsion test was applied using some specific test parameters to reproduce the same failure modes found in accelerated thermal cycling (ATC) test and in the field. In this paper, we present the torsion test parameters definition and two demonstrations of torsion test application to accelerate reliability characterization of second level interconnect. The first application is the comparison between full SnPb (tin–lead) and reballed LF (lead-free) packages using SnPb balls. In the second the reliability of ceramic BGA solder joints using different solder paste volume was evaluated. In both cases, ATC test results were used as reference. The results suggest that torsion test is a valuable test method and can be applied to evaluate the impact of design and process variations in very short time.

Thermal Fatigue of SnPb and SAC Resistor Joints: Analysis of Stress-Strain as a Function of Cycle Parameters

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. The relative effects of thermal cycling parameters (temperature range, dwell time, and ramp rate) and the failure mechanisms they induce have been the subject of many studies; however, uncertainty remains, particularly regarding the role of a very high ramp rate such as encountered in a thermal shock chamber. In the present research, thermomechanical finite-element (FE) models were used to analyze the stress/strain response of a resistor test vehicle during ATC testing under three accelerated test conditions: two ramp rates (14 degC/min and 95 degC/min) and two temperature ranges (DeltaT=0degC-100degC and -40degC-125degC), denoted 14-100 (ramp rate-temperature range), 95-100, and 95-165. The temperature gradients through the thickness of the assemblies were measured during the ATC test with the high ramp rate and were used to create an FE model that included transient stresses and strains. The effect of the transient temperature gradients during thermal shock was found to be negligible in these resistor joints. The FE models were then used to simulate the above three ATC test conditions with either SnPb or Pb-free (SAC) solders and were compared with previously published thermal fatigue lives for this resistor test vehicle. For both SnPb and SAC resistors, the maximum total solder strains (sum of elastic, plastic, and creep) and strain energy dissipation per cycle predicted by the FE models in the 95-165 test condition were much greater than those in either the 14-100 or 95-100 test conditions, which produced almost identical strains and energy dissipation. In all cases, the strain energy density dissipation per cycle due to creep was much larger than that due to plastic deformation. The trend of these results was in accordance with the ATC tests, which showed that the thermal cycling lives decreased in the same order for both the SAC and SnPb solders; i.e., the fatigue life decreased as the predicted total strain increased

Temperature profile effects in accelerated thermal cycling of SnPb and Pb-free solder joints

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC testing decreases life cycle test time by one or more of the following means: increasing the heating and cooling rate, decreasing the hold time, or increasing the range of the applied temperature. The relative effect of each of these cycle parameters and the failure mechanisms they induce has been the subject of many studies; however uncertainty remains, particularly regarding the role of the heating and cooling rate. In this research, three conditions with two ramp rates (14 °C/min and 95 °C/min) and two temperature ranges (Δ T = 0–100 °C and −40 to 125 °C) were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders. The test results showed that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference. For the resistors, the Pb-free solder joints lasted longer than the SnPb joints at the smaller Δ T, but were inferior at the larger Δ T. In contrast, the Pb-free solder joints in the PBGA test vehicles lasted longer than the SnPb solder under both conditions.