Abstract
A vast range of electronics products have utilized 2.5D packages for better performance and miniaturization. As multi-level assembly technologies are getting mature, 2.5D packaging technology becomes affordable. In this work, design guideline for board-level reliability of a 2.5D package was provided with respect to accelerated thermal cycling (ATC) and power cycling (PC). Finite element models were built and validated step-by-step by warpage measurement. Solder fatigue life in power cycling was investigated with temperature mapping technique merged into the process of scripting, which conducts load transfers from computational fluid dynamics (CFD) simulation to finite element analysis (FEA). ATC test was conducted with solder joint failure analysis. Fatigue life projection model was determined by correlation between tested life data and simulation results. Parametric studies regarding geometry factors and material properties were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. It is found that CTE mismatch between the substrate and the PCB is the major factor affecting board-level reliability in accelerated thermal cycling. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. Designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.
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