AC Negative Bias Temperature Instability Research Articles

Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.

Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ .

Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV+CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.

On the Circuit-Level Reliability Degradation Due to AC NBTI Stress

In this paper, an experimental analysis of the impact of dynamic negative bias temperature instability (NBTI) stress on the CMOS inverter dc response and temporal performance is presented. We analyzed the circuit behavior subjected to ac NBTI in the prospect to correlate the induced degradation with that seen at PMOS device level. The results revealed that, while ac NBTI-induced shift of the inverter features shows both voltage and temperature dependence, it does not always exhibit stress time dependence. Indeed, the time exponent $n$ is found to depend on both voltage and temperature. The analysis of such behavior when correlated with the PMOS threshold shift points toward the coexistence of more than one physical mechanism behind the degradation, where one mechanism could dominate the other under certain stress conditions. Depending on these conditions, circuit lifetime could be more or less affected.

A coarse-graining approach to rate equations of the composite AC-NBTI model

For ac negative bias temperature instability (NBTI), the composite model that combines the reaction–diffusion (R–D) model for permanent component and the trap–detrap (T–D) model for recoverable component has almost been accepted. However, simple analytical formulas, which are useful for product qualification, have not yet been established. In this paper, we present a coarse-graining approach to analyze the rate equations in the T–D and R–D schemes. Here, the time-averaged rate equations are derived from the equations for stress and recovery phases. The analytical solutions obtained by solving this set of equations can explain the essential features of ac-NBTI, such as the duty-cycle dependence and the memory effect of hole-trapping determined by the standby condition. For the T–D scheme, the exact analytical solutions of the original equations verify this approach, whereas for the R–D scheme, the double-interface R–D model rather than the conventional R–D model captures the duty-cycle dependence observed in the experimental universal curve. Our experimental data on the ac-NBTI are also consistent with the developed analytical model providing a general validity of the approach presented here.

Ultrafast AC–DC NBTI Characterization of Deep IL Scaled HKMG p-MOSFETs

Ultrafast DC and AC negative bias temperature instability (NBTI) measurements are done in high-k metal gate p-MOSFETs having deeply scaled interlayer. Time evolution of degradation during and after DC and AC stress at different duty cycle and frequency are characterized. Impact of last pulse cycle duration (half or full) and pulse low bias on AC stress are studied. Equivalence of measured data from large and small area devices are shown. Experimental results are qualitatively explained using known NBTI physical mechanism.

Essential aspects of Negative Bias Temperature Instability (NBTI)

We develop a comprehensive theoretical framework for explaining the key and characteristic experimental signatures of NBTI. The framework is based on an uncorrelated dynamics of interface-defect creation/annihilation described by Reaction-Diffusion (R-D) theory and hole trapping/detrapping into/out-of oxide defects based on a generalized Shockley-Read-Hall model. The proposed theory can consistently explain the long-term stress-phase power-law time exponent, stress/relaxation-phase temperature dependence, characteristic feature of duty-cycle dependence, and universal feature of frequency independence - measured in DC and AC stress conditions over a wide variety of transistors. Thus, we confirm the general validity of R-D theory in explaining the universal features (irrespective of dielectric material) of both DC and AC NBTI. The non-universal features of NBTI have correlation with the amount of oxide-defects within the dielectric and do not affect AC NBTI measurements at lower duty cycle. Decomposition of these (uncorrelated) universal and non-universal components is, therefore, essential before comparison with any theory.

A Modified Charge Pumping Method for Measuring Interface States Up to the Ghz Range

In this paper we present a modified on-chip charge pumping method for measuring the interface states in ultra-thin gate oxide complementary metal-oxide-semiconductor (CMOS) technology. The proposed method, which characterizes oxide interface states by applying pulse frequencies up to the GHz range, is used to evaluate the evolution of interface states due to dynamic negative bias temperature instability stress on the p-channel field-effect transistor (pFET). The results show that charge pumping increases linearly at frequencies up to the GHz range and that the time dependence of interface states due to AC negative bias temperature instability (NBTI) stress increases with a power law distribution. In addition, we demonstrate experimentally that the VTH shift due to AC NBTI stress depends on interface states and oxide traps.

Toward Understanding the Wide Distribution of Time Scales in Negative Bias Temperature Instability

Difficulties with evaluating Negative Bias Temperature Instability (NBTI) are linked to fast effects occurring at microsecond or possibly faster time scales. The wide distribution of time scales involved in NBTI relaxation suggests participation of some sort of dispersion in the underlying NBTI mechanism. A universal behavior of the relaxation is observed and used to benchmark several models incorporating dispersion. The impact of the boundary condition on the model based on dispersive transport is also briefly discussed. Furthermore, on-chip circuits are designed and fabricated to measure the effect of AC NBTI up to 2 GHz on individual devices. The results on both single pFET's and inverters indicate that AC NBTI is independent of the frequency in the entire 1 Hz - 2 GHz range. This suggests that any characteristic time scale of the NBTI mechanism must be below 1 ns.

Evaluation of negative bias temperature instability in ultra-thin gate oxide pMOSFETs using a new on-line PDO method

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID−VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction–diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90°C and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction–diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction–diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.