On the Circuit-Level Reliability Degradation Due to AC NBTI Stress

Abstract

In this paper, an experimental analysis of the impact of dynamic negative bias temperature instability (NBTI) stress on the CMOS inverter dc response and temporal performance is presented. We analyzed the circuit behavior subjected to ac NBTI in the prospect to correlate the induced degradation with that seen at PMOS device level. The results revealed that, while ac NBTI-induced shift of the inverter features shows both voltage and temperature dependence, it does not always exhibit stress time dependence. Indeed, the time exponent $n$ is found to depend on both voltage and temperature. The analysis of such behavior when correlated with the PMOS threshold shift points toward the coexistence of more than one physical mechanism behind the degradation, where one mechanism could dominate the other under certain stress conditions. Depending on these conditions, circuit lifetime could be more or less affected.