a-InGaZnO Thin-film Transistors Research Articles

Origin of the High Density of Oxygen Vacancies at the Back Channel of Back-Channel-Etched a-InGaZnO Thin-Film Transistors.

This study reveals the pronounced density of oxygen vacancies (Vo) at the back channel of back-channel-etched (BCE) a-InGaZnO (a-IGZO) thin-film transistors (TFTs) results from the sputtered deposition rather than the wet etching process of the source/drain metal, and they are distributed within approximately 25 nm of the back surface. Furthermore, the existence and distribution depth of the high density of Vo defects are verified by means of XPS spectra analyses. Then, the mechanism through which the above Vo defects lead to the instability of BCE a-IGZO TFTs is elucidated. Lastly, it is demonstrated that the device instability under high-humidity conditions and negative bias temperature illumination stress can be effectively alleviated by etching and thus removing the surface layer of the back channel, which contains the high density of Vo defects. In addition, this etch method does not cause a significant deterioration in the uniformity of electrical characteristics and is quite convenient to implement in practical fabrication processes. Thus, a novel and effective solution to the device instability of BCE a-IGZO TFTs is provided.

Gate bias stress reliability of a-InGaZnO TFTs under various channel dimension

In this work, we report a comprehensive and systematic study about the effect of various amorphous In-Ga-Zn-O (a-IGZO) channel dimensions on the gate bias stress reliability of a-IGZO thin film transistor (TFT) devices. The width of the channel is varied from 3, 10, 50 μm, while the length is varied from 3,5, 10 μm. There is a significant shift of Vth to negative voltage when the length is <10 μm and the width < 50 μm. The device is more stable when the length and width are increased to the optimal of 50 μm and 10 μm, respectively. At the optimal point, the Vth can get 0.54 V, and the Ion/Ioff ratio is 7.2 × 108. The field-effective mobility is 32 cm2/V.s, SS value is 0.15 V/dec. It shows a potential for variation in the a-IGZO channel dimension for enhancing the reliability of a-IGZO TFT devices.

Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress

Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress

Stably Saturated Output Current Characteristics and Hot-Carrier Reliability of a-InGaZnO Thin-Film Transistors With Source-Connected Field Plate

Stably Saturated Output Current Characteristics and Hot-Carrier Reliability of a-InGaZnO Thin-Film Transistors With Source-Connected Field Plate

Investigating an abnormal hump phenomenon in top gate a-InGaZnO thin-film transistors due to mobile sodium diffusion

Top gate a-InGaZnO (IGZO) thin-film transistors (TFTs) annealed at high temperature show excellent initial current–voltage (I–V) characteristics. However, when they are exposed to positive gate bias for a long time, hump can occur in the subthreshold region. This abnormal hump is accelerated at a higher positive gate voltage and mitigate by a negative gate voltage. While the strength of the hump is irrelevant to a change in channel width, it relies significantly on channel length. This phenomenon might be due to mobile Na ions diffused from a glass substrate migrating toward the back and edge side of the IGZO semiconductor by a vertical gate electric field. When a layer of Al2O3 is formed between the IGZO semiconductor and the glass substrate, the hump phenomenon could be successfully solved by serving as a barrier for Na ions moving into the IGZO.

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination.

In this work, an electrical stability model based on surface potential is presented for amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) under positive-gate-bias stress (PBS) and light stress. In this model, the sub-gap density of states (DOSs) are depicted by exponential band tails and Gaussian deep states within the band gap of a-IGZO. Meanwhile, the surface potential solution is developed with the stretched exponential distribution relationship between the created defects and PBS time, and the Boltzmann distribution relationship between the generated traps and incident photon energy, respectively. The proposed model is verified using both the calculation results and experimental data of a-IGZO TFTs with various distribution of DOSs, and a consistent and accurate expression of the evolution of transfer curves is achieved under PBS and light illumination.

Channel migration of dual channel a-InGaZnO TFTs under negative bias illumination stress

In this work, the time-dependent behaviors of dual-channel amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under negative bias illumination stress (NBIS) are systematically discussed. The dual-channel comprised two different IGZO layers fabricated by tuning the oxygen flow during deposition. The presence of heterojunctions enhanced field-effect mobility by 1.5× owing to the confinement of carriers in buried channels because of an energy barrier. However, after long periods of NBIS stress, the degradation of a-IGZO TFTs resulted in the entrapment of photo-generated electron–hole pairs at interface defects. The conduction path migrated to the surface channel. Results from extracting the hysteresis window and utilizing capacitance–voltage measurements have indicated a channel migration phenomenon due to the entrapment of electrons and holes at the surface and buried channel interfaces.

Reduced Dynamic Gate Pulse Stress Instability in Dual Gate a-InGaZnO Thin Film Transistors

The dynamic gate pulse stress effect on the electrical performance of single gate (SG) and dual gate (DG) thin-film transistors (TFTs) is reported. The stress is implemented with rising and falling pulses of 1 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.1 ~\mu \text{s}$ </tex-math></inline-formula> respectively with positive gate pulse (0 to +30V). The DG TFT under slow switching ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{s}$ </tex-math></inline-formula> ) shows stable TFT performance with a small threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text{TH}}$ </tex-math></inline-formula> ) of 1.3 V than SG TFT ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text{TH}}$ </tex-math></inline-formula> of 2.4 V) for 24 h stress at room temperature. Under a fast switching of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.1 ~\mu \text{s}$ </tex-math></inline-formula> , DG TFT exhibits a 1.8 V shift, and SG TFT shows a 3.0 V shift. The recovery behavior of the transfer curves is also checked by keeping the TFTs unbiased for 24 h after applying stress, resulting in the DG TFTs showing complete recovery while SG TFTs exhibiting partial recovery. The lifetime of DG TFTs is found to be 7.5 times longer than that of SG TFTs under dynamic gate pulse stress.

A Simple Intermediate Approach of Sputter Deposition at Room Temperature for Improving the Stability of a-InGaZnO Thin Film Transistors

A Simple Intermediate Approach of Sputter Deposition at Room Temperature for Improving the Stability of a-InGaZnO Thin Film Transistors

An Analytical Surface Potential and Effective Charge Density Approach Based Drain Current Model for Amorphous InGaZnO Thin-Film Transistors

An analytical surface-potential-based drain current model for amorphous indium–gallium–zinc–oxide (a-InGaZnO) thin film transistors (TFTs) is proposed by introducing an effective charge density approach in this paper. This approach gives two initial approximate values of the effective state density and the effective thermal voltage by using the dominant state of the free charge density in total charge density, and then obtains a high-precision one-exponent equivalent transformation for three-exponent total charge density. Based on this approach, we have solved the problem that the physical meaning of the transition area in the regional method is not clear and a one-piece analytical surface potential solution to Poisson’s equation is successfully derived. Furthermore, the drain current is also explicitly derived from the charge sheet model and I-V characteristics of a-InGaZnO TFTs are reproduced from the above obtained model. Finally, accurate and effective surface-potential model and drain current model are obtained and verified by experimental data, respectively. Good verification results prove that the proposed model could become an accurate and suitable tool for being embedded into a circuit simulation.

Artificial Synaptic InGaZnO Thin-Film Transistor With Long Retention Behavior Using Al2O3/SiO2 Gate Insulator

We present a coplanar amorphous InGaZnO (a-IGZO) synaptic thin film transistor (TFT) with counterclockwise hysteresis using an aluminum oxide (Al2O3)/SiO2 gate insulator (GI). The excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), short-term plasticity (STP), and long-term plasticity, which are biological synaptic characteristics, are demonstrated by positive charge trapping in the Al2O3 layer. Long retention time can be possible by surface charge in the SiO2, a charge-blocking layer. As a result, multi-level channel conductance can be modulated with positive and negative gate pulses. These results prove synaptic a-InGaZnO TFT with Al2O3/SiO2 stack GI for high-density neuromorphic devices.

Abnormal Subthreshold Swing Decrease in a-InGaZnO Thin-Film Transistor After Self-Heating Stress

This study investigates abnormal decreased subthreshold swing (S.S.) and increased <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> in back-channel etch (BCE) InGaZnO (IGZO) thin-film transistors (TFTs) under self-heating stress (SHS) operation. With confirmation of the energy band diagram via gate-to-source ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GS}}$ </tex-math></inline-formula> ) and gate-to-drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GD}}$ </tex-math></inline-formula> ) measurements of the capacitance–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> ) curve, the degradation mechanism is further inferred. The degradation arises from uneven trapped charges by the thermal field. To illustrate the mechanism, the device with uneven trapped charges and the double-gate device with different values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> are simulated by SILVACO-TCAD.

One-Step Synergistic Treatment Approach for High Performance Amorphous InGaZnO Thin-Film Transistors Fabricated at Room Temperature.

Amorphous InGaZnO (a-InGaZnO) is currently the most prominent oxide semiconductor complement to low-temperature polysilicon for thin-film transistor (TFT) applications in next-generation displays. However, balancing the transmission performance and low-temperature deposition is the primary obstacle in the application of a-InGaZnO TFTs in the field of ultra-high resolution optoelectronic display. Here, we report that a-InGaZnO:O TFT prepared at room temperature has high transport performance, manipulating oxygen vacancy (VO) defects through an oxygen-doped a-InGaZnO framework. The main electrical properties of a-InGaZnO:O TFTs included high field-effect mobility (µFE) of 28 cm2/V s, a threshold voltage (Vth) of 0.9 V, a subthreshold swing (SS) of 0.9 V/dec, and a current switching ratio (Ion/Ioff) of 107; significant improvements over a-InGaZnO TFTs without oxygen plasma. A possible reason for this is that appropriate oxygen plasma treatment and room temperature preparation technology jointly play a role in improving the electrical performance of a-InGaZnO TFTs, which could not only increase carrier concentration, but also reduce the channel-layer surface defects and interface trap density of a-InGaZnO TFTs. These provides a powerful way to synergistically boost the transport performance of oxide TFTs fabricated at room temperature.

Abnormal Hump and Two-Step Degradation of Top Gate a-InGaZnO TFTs Under Positive Bias Stress

In this study, the electrical characteristics of top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress (PBS) are investigated. Abnormal two-step degradation and hump effects are observed under PBS. When the self-aligned process is applied during the interlayer dielectric (ILD) deposition, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> IGZO is formed by hydrogen doping to define the source and drain, which is accompanied by hydrogen diffusion not only into the channel to influence the initial electrical performance but also into the gate insulator (GI), which leads to the degradation under PBS. The diffusion distance in the length and width directions is calculated. Also, the differences in the diffusion distance in the width and length directions can be ascribed to the geometric structure of the top-gate a-IGZO TFTs. The hump occurs after PBS because of the impact of hydrogen diffusion in the width direction. The two-step degradation and its sequences can be ascribed to two mechanisms, including electron trapping and hydrogen diffusion.

Competition between heating and cooling during dynamic self-heating degradation of amorphous InGaZnO thin-film transistors

The dynamic self-heating (SH) instability of a-InGaZnO (a-IGZO) thin-film transistors (TFTs) was systematically investigated under static drain bias and pulsed gate voltage. The a-IGZO TFTs exhibited three distinct degradation stages, including a slightly positive shift of threshold voltage (ΔVth), then a gradually negative ΔVth, and finally an accelerated negative shift leading to normally-on characteristics. The underlying mechanisms were clarified to be SH-enhanced positive bias stress (PBS) instability, SH-generated donor defects, and the donor-populated central channel, respectively. By changing the duty ratio, frequency, peak, and base periods of gate pulses. The competition between heating and cooling periods was found to dominate the behavior and degree of dynamic SH degradations, suggesting a feasible instability-relieving method by sophisticatedly adjusting the dynamic operating conditions.

Self-Compensation Effect of Photo-Bias Instabilities in a-InGaZnO Thin-Film Transistors Induced by Unique Ion Migration

The a-InGaZnO (a-IGZO) thin-film transistors (TFTs) in elevated-metal metal-oxide (EMMO) architecture was found to exhibit high stability against photo-bias stresses. In contrast to the common photo-enhanced degradation, an abnormal self-compensation effect of photo-bias instabilities was first observed for amorphous oxide semiconductor (AOS) TFTs. By analyzing the defect states and element distributions in both channel and source/drain (S/D) regions, the unique migration of thermally generated metal interstitials in a-IGZO S/D was clarified to be the origin. More specifically, the positive bias stress (PBS)-induced negative shift of threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> ) originates from the ionization of positive metal ions near the backchannel, while these positively charged ions can be compensated by the illumination-excited electrons, resulting in photo-stable AOS TFTs. This also provides a flexible way to implement the electrically stable depletion-mode AOS TFTs.

Degradation mechanisms for a-InGaZnO thin-film transistors functioning under simultaneous DC gate and drain biases

Degradation of a-InGaZnO thin-film transistors working under simultaneous DC gate and drain bias stress is investigated, and the corresponding degradation mechanism is proposed and verified. The maximum degradation occurs under the bias stress condition that makes the electric field and electron concentration relatively high at the same time. Trapping of hot electrons in the etching-stop layer under the extended drain electrode is proven to be the underlying mechanism. The observed degradation phenomena, including distortion in the transfer curve on a logarithmic scale and two-slope dependence on gate bias on a linear scale, current crowding in the output curve, and smaller degradation in transfer curves measured under large drain bias, can all be well explained with the proposed degradation mechanism.

Roles of Hot Carriers in Dynamic Self-Heating Degradation of a-InGaZnO Thin-Film Transistors

The dynamic self-heating (SH) degradation was investigated on a-InGaZnO (a-IGZO) thin-film transistors (TFTs) under constant drain bias and varied gate pulses. Besides the negative shift of threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {th}}}$ </tex-math></inline-formula>), similar with that under DC SH stress, the asymmetric degradations near drain and source revealed the concomitant hot-carrier (HC) effect. The HC-induced local barrier near drain could compensate certain SH-induced <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {th}}}$ </tex-math></inline-formula> shift, while a drastic SH effect would in turn enhance the HC barrier to high enough to cause hard breakdown. For a-IGZO TFTs under dynamic SH stresses, the interactions between SH and HC effects dominate the degradation behaviors and can be sensitively tuned by the falling time of gate pulse, suggesting a feasible method of lessening the dynamic instability.

Abnormal Bias Instabilities Induced by Lateral H2O Diffusion Into Top-Gate Insulator of a-InGaZnO Thin-Film Transistors

The environmental stability of self-aligned top-gate (SATG) a-InGaZnO thin-film transistor (TFT) was studied by performing the high-temperature high-humidity (HTHH) test. Despite the maintenance of initial electrical characteristics, the stability under positive bias stress (PBS) was considerably deteriorated, including an abnormal negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\mathrm{ th}}$ </tex-math></inline-formula> shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\Delta } {V} _{\mathrm{ th}}$ </tex-math></inline-formula> ), increased off current, and degraded <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</i> . Moreover, the negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V} _{\mathrm{ th}}$ </tex-math></inline-formula> was consistently enhanced with the channel length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> ) decreasing. Such <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> dependence was clarified to originate from the lateral diffusion of H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O in TG insulator during HTHH tests, and the PBS instabilities were caused by the ionization and migration of H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O molecules into the a-IGZO channel, as verified by the X-ray photoelectron spectroscopy, C-V characteristics, and recovery behaviors of PBS degradation.

Effects of Ambient/Carrier Gas on Amorphous InGaZnO-Based Thin-Film Transistors Using Ultrasonic Spray Pyrolysis Deposition

This study investigates how ambient/carrier gases affect the material characteristics of amorphous indium-gallium-zinc oxide (a-InGaZnO) thin films deposited using the ultrasonic spray pyrolysis deposition (USPD) method. Nitrogen and air are used as the ambient/carrier gases in this study. The crystallinity, oxygen deficiency, energy bandgap, and trap level in the a-InGaZnO thin films are analyzed. The performance of the thin-film transistors (TFTs) based on a-InGaZnO with different ambient/carrier gases is investigated as well. It is found that oxygen deficiency is suppressed when air is used as the ambient/carrier gas. When nitrogen is used as the ambient/carrier gas to deposit a-InGaZnO thin film, the TFT shows higher field-effect mobility and saturation mobility. However, when the a-InGaZnO thin film is deposited with air as the ambient/carrier gas, the subthreshold swing, ON-/ OFF-current ratio, interface trap density, and stability of the TFT are improved. This study demonstrates how ambient/carrier gases in the USPD system affect the performance of a-InGaZnO TFT.