Gate bias stress reliability of a-InGaZnO TFTs under various channel dimension

Abstract

In this work, we report a comprehensive and systematic study about the effect of various amorphous In-Ga-Zn-O (a-IGZO) channel dimensions on the gate bias stress reliability of a-IGZO thin film transistor (TFT) devices. The width of the channel is varied from 3, 10, 50 μm, while the length is varied from 3,5, 10 μm. There is a significant shift of Vth to negative voltage when the length is <10 μm and the width < 50 μm. The device is more stable when the length and width are increased to the optimal of 50 μm and 10 μm, respectively. At the optimal point, the Vth can get 0.54 V, and the Ion/Ioff ratio is 7.2 × 108. The field-effective mobility is 32 cm2/V.s, SS value is 0.15 V/dec. It shows a potential for variation in the a-IGZO channel dimension for enhancing the reliability of a-IGZO TFT devices.