a-IGZO Thin-film Transistors Research Articles

Performance Improvement of Self-Aligned Coplanar Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors by Boron Implantation

The electrical properties and device stability of a self-aligned (SA) coplanar amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) were investigated by implanting boron (B) into the source/drain (SD) n+ region. To evaluate the effect according to the depth profile of B in the a-IGZO film, various implantation energies were applied. The electrical properties were optimized when the projection range of B was in the central vertical region of the a-IGZO film. B implantation decreased the resistivity of the a-IGZO film from 3.1 × 102 to 2.1 × 10–3 Ω·cm compared to an untreated a-IGZO film, while the field-effect mobility (μfe) improved from 2.96 to 17.22 cm2/(V·s). Moreover, the fabricated SA coplanar a-IGZO TFTs with a B-doped n+ region exhibited excellent stability, with a threshold voltage shift (ΔVth) of <0.2 V during a 3000 s thermal stability test performed at 200 °C and a bias stress test under a gate voltage of ±20 V. During the implantation process, B ions with high kinetic energy collide with IGZO atoms, resulting in the formation of an oxygen vacancy (VO) and an oxygen interstitial (Oi) simultaneously. The implanted B ions and Oi are bonded such that the VO sites are maintained by the B–O reaction and can contribute to an increase in the carrier concentration in a-IGZO films, thereby increasing the conductivity of the n+ region.

Analysis of Nitrogen-Doping Effect on Sub-Gap Density of States in a-IGZO TFTs by TCAD Simulation.

In this work, the impact of nitrogen doping (N-doping) on the distribution of sub-gap states in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is qualitatively analyzed by technology computer-aided design (TCAD) simulation. According to the experimental characteristics, the numerical simulation results reveal that the interface trap states, bulk tail states, and deep-level sub-gap defect states originating from oxygen-vacancy- (Vo) related defects can be suppressed by an appropriate amount of N dopant. Correspondingly, the electrical properties and reliability of the a-IGZO TFTs are dramatically enhanced. In contrast, it is observed that the interfacial and deep-level sub-gap defects are increased when the a-IGZO TFT is doped with excess nitrogen, which results in the degeneration of the device’s performance and reliability. Moreover, it is found that tail-distributed acceptor-like N-related defects have been induced by excess N-doping, which is supported by the additional subthreshold slope degradation in the a-IGZO TFT.

Enhanced Electrical Performance and Bias Stability of a-IGZO Thin-Film Transistor by Ultrasonicated Pre-annealing

Vacuum-processed oxide semiconductors have enabled incredible recent advances in the scientific research of metal oxide thin-film transistors (TFTs) and their introduction in commercial displays. Developing metal oxide transistors with low processing temperatures, on the other hand, remains a challenge. Metal oxide transistors are commonly produced at high processing temperatures (over 500°C) and have a high working voltage (30~50 V). Here, we introduce amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs that show enhanced electrical characteristics, environmental stability, and switching behavior, prepared using ultrasonicated pre-annealing. Before post-annealing, the ultrasonication treatment was given at 40 kHz for 20 minutes. The improved electrical characteristics of this ultrasonicated a-IGZO TFTs were: 10.78 cm&lt;sup&gt;2&lt;/sup&gt;/Vs; 1.2×10&lt;sup&gt;7&lt;/sup&gt; on/off current ratio. The a-IGZO TFTs with ultrasonicated pre-annealing were also extremely stable under a variety of stresses. For an ultrasonicated a-IGZO TFT, the threshold voltage (&lt;i&gt;Vth&lt;/i&gt;) shifted by +0.82 V in a positive bias stress test and -0.30 V in a negative bias stress test. This means that the sonication treatment improves both electrical and surface morphological qualities, while also lowering faults by eliminating contaminants from the a-IGZO channel layer's surface and preventing atomic rearrangement. Furthermore, the dynamic response characteristics were measured according to frequency. A dynamic inverter test was carried out at 1 kHz frequency, with the load resistance of the circuit set to 10 MW and the drain supply voltage set to 5 V (&lt;i&gt;VDD&lt;/i&gt;).

Robust Mobility Enhancement and Comprehensive Reliability Evaluation for Amorphous InGaZnO TFT by Double Layers With Quantum Well Structures

Mobility enhancement is an important research topic for amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) since it is directly related to the device&#x2019;s performance. The double-layer a-IGZO channel with quantum well structure was proposed for mobility enhancement. However, the impact of such double layers with the quantum well structure on a-IGZO TFT reliabilities, i.e., positive bias temperature stress (PBTS) and negative bias temperature illumination stress (NBTIS), is still elusive. In this work, the mobility enhancement by double layers with quantum well structures is proven to be robust in mass production Gen 8.5 line. Then, the a-IGZO TFT under PBTS and NBTIS is investigated systematically. The variations of mobility <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>, subthreshold slope SS, and threshold voltage shift <inline-formula> <tex-math notation="LaTeX">${\Delta {V}_{\text {th}}}$ </tex-math></inline-formula> with PBTS and NBTIS stress time are evaluated and analyzed, respectively. It is shown that the double-layer a-IGZO channel with quantum well structure can sustain as good reliability performance as the reference single-layer device.

Gate Driver Circuit Based on Depletion-Mode Indium-Gallium-Zinc Oxide Thin-Film Transistors Using Capacitive Coupling Effect

This article proposes a highly reliable gate driver circuit based on amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). The proposed circuit adopted an additional boosted-down structure to maintain the control node (Q-node) of the output TFTs at a low voltage level using the capacitive coupling effect instead of the TFT structure. Consequently, the proposed circuit exhibited stable operation for depletion-mode TFTs with a threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) of −3 V. The boosted-down structure improved the operation reliability because it reduced the current flow from Q-node to low-level voltage node by removing the continuously degraded TFTs. The drain–source voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> ) stress on the TFTs connected to the Q-node was reduced by separating these TFTs from the Q-node during bootstrapping. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> value during Q-node bootstrapping was reduced from 44.3 to 27.3 V. A pull-down TFT was designed to operate with a 50% duty ratio to ensure reliability against the bias stress. The output node was discharged by the Q-node discharging TFTs in the next stage during the remaining 50% period. Therefore, the output node was discharged with a total duty ratio of 100%. The proposed circuit operated stably as a shift register with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> varying from −3 to 9 V. Consequently, using capacitive coupling effect, the proposed circuit exhibited reliable operation with depletion- and enhancement-mode a-IGZO TFTs.

Ultraviolet-Assisted Low-Thermal-Budget-Driven α-InGaZnO Thin Films for High-Performance Transistors and Logic Circuits.

Developing a low-temperature fabrication strategy of an amorphous InGaZnO (α-IGZO) channel layer is a prerequisite for high-performance oxide-based thin film transistor (TFT) flexible device applications. Herein, an ultraviolet-assisted oxygen ambient rapid thermal annealing method (UV-ORTA), which combines ultraviolet irradiation with rapid annealing treatment in an oxygen atmosphere, was proposed to realize the achievement of high-performance α-IGZO TFTs at low temperature. Experimental results have confirmed that UV-ORTA treatment has the ability to suppress defects and obtain high-quality films similar to high-temperature-annealing-treated samples. α-IGZO/HfAlO TFTs with high-performance and low-voltage operating have been achieved at a low temperature of 180 °C for 200 s, including a high μsat of 23.12 cm2 V-1 S-1, large Ion/off of 1.1 × 108, small subthreshold swing of 0.08 V/decade, and reliable stability under bias stress, respectively. As a demonstration of complex logic applications, a low-voltage resistor-loaded unipolar inverter based on an α-IGZO/HfAlO TFT has been built, demonstrating full swing characteristics and a high gain of 13.8. Low-frequency noise (LFN) characteristics of α-IGZO/HfAlO TFTs have been presented and concluded that the noise source tended to a carrier number fluctuation (ΔN) model from a carrier number and correlated mobility fluctuation (ΔN-Δμ) model. As a result, it can be inferred that the low-temperature UV-ORTA technique to improve α-IGZO thin film quality provides a facile and designable process for the integration of α-IGZO TFTs into a flexible electronic system.

Hydrogen incorporation into amorphous indium gallium zinc oxide thin-film transistors

An experimental study is conducted in which the subgap trap density of states (DoS) is measured by ultrabroadband photoconduction (UBPC) to examine hydrogen incorporation into the channel layer of top-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). UBPC reveals that hydrogen incorporation leads to the creation of a spectrally broad (∼0.3 eV FWHM) distribution of electronic states in the bandgap centered at 0.4 eV above the valence band mobility edge and to an increase in valence band tail state density. Concomitantly, drain current–gate voltage transfer curves demonstrate that hydrogen incorporation results in a negative shift in the turn-on voltage. Quantitatively, electronic state densities estimated by UBPC and the turn-on voltage shift are identical. These experimental findings imply that hydrogen acts as a donor in a-IGZO, but that its donor ionization energy is extraordinarily large, i.e., ∼2.8 eV, inconsistent with that of a normal donor. It is proposed that this anomalous donor behavior is a consequence of the negative-U property of hydrogen in a-IGZO in which hydrogen ionization precedes its incorporation into the lattice network.

Highly Reliable Flexible Device with a Charge Compensation Layer.

Flexible devices fabricated with a polyimide (PI) substrate are essential for foldable, rollable, and stretchable products and various applications. However, inherent technical challenges remain in mobile charge-induced device instabilities and image retention, significantly hindering future technologies. Here, we introduce a new barrier material, SiCOH, into the backplane of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) and applied it to production-level flexible panels. We found that the SiCOH layer effectively compensates for the surface charging induced by fluorine ions at the interface between the PI substrate and the barrier layer under bias stress, thereby preventing abnormal positive shifts in threshold voltage (Vth) and image disturbance. The a-IGZO TFTs and metal-insulator-metal and metal-insulator-semiconductor capacitors with a SiCOH layer demonstrate reliable device performance, Vth shifts, and capacitance changes with an increase in gate bias stress. A flexible device with SiCOH enables the suppression of abnormal Vth shifts associated with PIs and plays a vital role in image sticking. This work provides new insights into process integrity and paves the way for expediting versatile form factors.

The effect of passivation-layer process to amorphous InGaZnO thin-film transistors using back-channel etch method

In this work, based on the channel damage caused by source/drain etching and passivation-layer deposition, the effects of the passivation-layer process on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) devices were studied by combining experimental investigation with simulation verification. In terms of experimental exploration, it was found that the back-channel N2O plasma treatment had a significant impact on the performance of the device, which was difficult to control. Hence, to achieve a low cost, the entire back-channel process was directly carried out as two steps of SiO x passivation-layer deposition and final thermal annealing. In the aspect of simulation verification, the influence of the passivation-layer deposition radio-frequency (RF) power and the annealing effect on the internal mechanism of the device was studied based on a high-concentration doped defect density of states (DOS) model (doping level was N D = 1020 cm−3). The experimental results demonstrated that the high-performance of an a-IGZO TFT device can be achieved by adjusting the RF power of SiO x passivation-layer deposition. It was more important that annealing after passivation-layer deposition was a critical step in the manufacture of high-performance TFTs. The device exhibited the ideal performance after annealing under 1000 W RF power, with a threshold voltage of 5.65 V, a saturation mobility of 12.87 cm2 V−1s−1, a subthreshold swing of 0.88 V dec−1, and a current on-off ratio of 2.62 × 10°8. In addition, using the DOS model, it was found that the SiO x passivation-layer process had a significant impact on the DOS distribution and the carrier distribution in the channel, which in turn caused the threshold voltage to drift. At last, the high uniformity and stability of an a-IGZO TFTs array on glass were characterized.

Migration of weakly bonded oxygen atoms in a-IGZO thin films and the positive shift of threshold voltage in TFTs

Amorphous indium-gallium-zinc oxide (a-IGZO) thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor (TFT) devices. In-situ x-ray photoelectron spectroscopy (XPS) illustrates that weakly bonded oxygen (O) atoms exist in a-IGZO thin films deposited at high O2 pressures, but these can be eliminated by vacuum annealing. The threshold voltage (V th) of the a-IGZO TFTs is shifted under positive gate bias, and the V th shift is positively related to the deposition pressure. A temperature variation experiment in the range of 20 K–300 K demonstrates that an activation energy of 144 meV is required for the V th shift, which is close to the activation energy required for the migration of weakly bonded O atoms in a-IGZO thin films. Accordingly, the V th shift is attributed to the acceptor-like states induced by the accumulation of weakly bonded O atoms at the a-IGZO/SiO2 interface under positive gate bias. These results provide an insight into the mechanism responsible for the V th shift of the a-IGZO TFTs and help in the production of reliable designs.

Ultra-Low Power, Emission Gate Driver With Pulse Width Modulation Using Low-Temperature Poly-Si Oxide Thin-Film Transistors

We report a novel emission gate driver using low- temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The proposed circuit consists of eight p-type low-temperature poly-Si (LTPS) and four n-type amorphous InGaZnO (a-IGZO) TFTs. The output pulse width is adjustable by changing the position of starting control signal which has constant pulse width without additional clock signals. The emission gate driver releases the output signals with various duty ratios. Excellent gate driving performance is achieved from the LTPO emission gate driver, although the a-IGZO TFTs have the threshold voltage of −5.5 V. In addition, the power consumption is as low as 5.98 mW in case of 80 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{s}$ </tex-math></inline-formula> pulse, 10 times of gate pulse, at refresh rate of 120 Hz with full high-definition ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1920\times1080$ </tex-math></inline-formula> ) for active-matrix organic light- emitting diode (AMOLED) display.

Investigation of Hump Behavior of Amorphous Indium-Gallium-Zinc-Oxide Thin-Film Transistor Under Positive Bias Stress

We investigate positive bias stress (PBS)-induced hump behavior in the subthreshold current region of the transfer characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). We analyze the origin of hump creation as parasitic edge conduction using both experiment and simulation. Based on the simulated results, we confirm that an additional narrow (~0.1 eV), Gaussian (~2.94 eV) trap states away from valance band maximum (VBM) is created within the parasitic channel after the PBS. A sharp decrease in the active layer thickness at the edge region of the active layer during the fabrication process increases the electric field during PBS which resulted in the creation of shallow oxygen vacancies at the edge region. As a result, a higher electron concentration at parasitic conduction path turned on the transistor earlier causing hump behavior in the subthreshold region of the transfer curve. Moreover, the increase of various distances between the main channel and the parasitic transistor is also simulated. It is identified that the extended width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W_{E}$ </tex-math></inline-formula> ) of the active layer ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.5 ~\mu \text{m}$ </tex-math></inline-formula> when compared to the main channel exhibits a significant difference in the conduction current than the parasitic channel and the main channel current is not affected anymore by parasitic conduction which efficiently eliminates the hump.

The Influence of Climate Conditions and On-Skin Positioning on InGaZnO Thin-Film Transistor Performance

Thin-film transistors (TFTs) based on amorphous indium-gallium-zinc-oxide (a-IGZO) have proved promising features for flexible and lightweight electronics. To achieve technological maturity for commercial and industrial applications, their stability under extreme environmental conditions is highly required. The combined effects of temperature (T) from −30.0°C to 50.0°C and relative humidity (RH) stress from 0 to 95% on a-IGZO TFT is presented. The TFT performances and the parameters variation were analysed in two different experiments. First, the TFT response was extracted while undergoing the most extreme climate conditions on Earth, ranging from the African Desert (50.0°C, 22%) to Antarctic (−30.0°C, 0%). Afterwards, the device functionality was demonstrated in three parts of the human body (forehand, arm and foot) at low (35%), medium (60%) and high (95%) relative humidity for on-skin and wearable applications. The sensitivity to T/RH variations suggests the suitability of these TFTs as sensing element for epidermal electronics and artificial skin.

High-Performance a-IGZO TFT Fabricated With Ultralow Thermal Budget via Microwave Annealing

In this work, we report high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with atomic layer deposited Al₂O₃ dielectric processed at a minimal temperature of 189.6 &#x00B0;C via microwave annealing (MWA). The a-IGZO TFT with MWA exhibits an improvement of 57&#x0025; in subthreshold swing (SS) compared with the unannealed device; meanwhile, it retains high field-effect mobility of up to 29.2 cm²/(V <inline-formula> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s) and large switching ratio of &#x003E;10⁸. Moreover, the SS of the device was further reduced through a two-step MWA treatment. It is believed that MWA treatment effectively reduces the density of trap states associated with oxygen vacancies, promotes the formation of lattice oxygen, and thus improves the quality of IGZO film. MWA with low thermal budget shows great potential in applications of the back-end of line (BEOL)-compatible oxide devices.

Roles of Hot Carriers in Dynamic Self-Heating Degradation of a-InGaZnO Thin-Film Transistors

The dynamic self-heating (SH) degradation was investigated on a-InGaZnO (a-IGZO) thin-film transistors (TFTs) under constant drain bias and varied gate pulses. Besides the negative shift of threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {th}}}$ </tex-math></inline-formula>), similar with that under DC SH stress, the asymmetric degradations near drain and source revealed the concomitant hot-carrier (HC) effect. The HC-induced local barrier near drain could compensate certain SH-induced <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {th}}}$ </tex-math></inline-formula> shift, while a drastic SH effect would in turn enhance the HC barrier to high enough to cause hard breakdown. For a-IGZO TFTs under dynamic SH stresses, the interactions between SH and HC effects dominate the degradation behaviors and can be sensitively tuned by the falling time of gate pulse, suggesting a feasible method of lessening the dynamic instability.

Influence of high-k dielectric material on the electrical performance of a-IGZO Thin Film Transistor

Here, the electrical performance of an amorphous Indium Gallium Zinc Oxide (a-IGZO) Thin Film Transistor (TFT) is examined using the Silvaco Atlas tool. The effects of several factors such as drain current (Id), Sub threshold Swing (SS), IonIoff, threshold voltage (Vth), on voltage (Von) are closely examined. When SiO2 was replaced by high-k HfO2, TFT shows low SS of 0.17 V/decade, high IonIoff ratio of ∼1018 and Von of 0.13 V. Effect of channel length is also analysed for high-k Al2O3 dielectric. This analysis might be useful for researchers to realize future TFT related applications.

Amorphous IGZO Thin-Film Transistor Gate Driver in Array for Ultra-Narrow Border Displays

A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays. In the design, each TFT in the gate driver circuits is divided into a certain number of smaller size devices, which can be placed in different subpixels. Therefore, the pixel aperture ratio loss is minimized, and uniform placement of the gate driver circuits over the pixel array area is able to be achieved. The proposed step-like repeating block structure further reduces the occupied area of the signal interconnects. A 12.4-inch fringe field switching (FFS) liquid crystal display (LCD) panel of ultra-narrow border (0.5 mm) is demonstrated with reliable operation based on this GIA design, proving its potential for practical applications.

Performance Improvement by Double-Layer a-IGZO TFTs With a Top Barrier

The double-layer a-IGZO thin film transistors (DL-TFTs) using a quantum well channel and a top barrier can reduce the subthreshold swing and hysteresis by 0.73 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> and 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> , respectively, in the transfer characteristics using the bottom gate sweep as compared to the single-layer TFTs (SL-TFTs). The wide bandgap barrier on top of the narrow bandgap IGZO channel serves as a protection layer between the IGZO channel and the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> top gate insulator to prevent plasma-induced damage on the IGZO channel caused by the S/D metal etching and the top gate insulator deposition. As for the mobility using the bottom gate operation with the top gate grounded, the DL-TFTs show higher mobility (1.06 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> ) at the room temperature due to less Coulomb scattering caused by the plasma-induced damage for percolation conduction, while the SL-TFTs have higher mobility at low temperatures due to the improved hopping efficiency for thermally activated hopping. The hysteresis is temperature independent down to 160 K, indicating the electrons tunneling between the channel and the top gate insulator is dominant. As for the reliability, DL-TFT has a smaller V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift than SL-TFT under both positive bias temperature stress (PBTS) due to less subgap defect in the channel.

Tailoring the synaptic properties of a-IGZO memristors for artificial deep neural networks

Neuromorphic computation based on resistive switching devices represents a relevant hardware alternative for artificial deep neural networks. For the highest accuracies on pattern recognition tasks, an analog, linear, and symmetric synaptic weight is essential. Moreover, the resistive switching devices should be integrated with the supporting electronics, such as thin-film transistors (TFTs), to solve crosstalk issues on the crossbar arrays. Here, an a-Indium-gallium-zinc-oxide (IGZO) memristor is proposed, with Mo and Ti/Mo as bottom and top contacts, with forming-free analog switching ability for an upcoming integration on crossbar arrays with a-IGZO TFTs for neuromorphic hardware systems. The development of a TFT compatible fabrication process is accomplished, which results in an a-IGZO memristor with a high stability and low cycle-to-cycle variability. The synaptic behavior through potentiation and depression tests using an identical spiking scheme is presented, and the modulation of the plasticity characteristics by applying non-identical spiking schemes is also demonstrated. The pattern recognition accuracy, using MNIST handwritten digits dataset, reveals a maximum of 91.82% accuracy, which is a promising result for crossbar implementation. The results displayed here reveal the potential of Mo/a-IGZO/Ti/Mo memristors for neuromorphic hardware.

Interface scattering dominated carrier transport in hysteresis-free amorphous InGaZnO thin film transistors with high-k HfAlO gate dielectrics by atom layer deposition

In this work, we systematically investigated the carrier transport of hysteresis-free amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) incorporating high-k (HfO2) x (Al2O3) y gate dielectrics with different composition and permittivity by atomic layer deposition. A dielectric surface morphology dominated interface scattering carrier transport mechanism is demonstrated, and the effect of the dielectric polarization and the interface states on the carrier mobility is discovered in TFT devices gated by high quality dielectrics with negligible charge trap effect. Accordingly, an a-IGZO TFT gated by (HfO2)0.5(Al2O3)0.5 dielectric with the smoothest surface exhibits the best performance in terms of a preferable field-effect mobility of 18.35 cm2 V−1 s−1, a small subthreshold swing of 0.105 V decade−1, a high on/off current ratio of 4.6 × 106, and excellent stability under positive bias stress.