Performance Improvement by Double-Layer a-IGZO TFTs With a Top Barrier

Jih-Chao Chiu,Cheng-Hsu Chou,C W Liu,Ming-Xuan Lee,Chia-Chun Yen,Song-Ling Li,Tsang-Long Chen

doi:10.1109/jeds.2021.3130211

Jih-Chao Chiu, Cheng-Hsu Chou + Show 5 more

Open Access

https://doi.org/10.1109/jeds.2021.3130211

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Abstract

The double-layer a-IGZO thin film transistors (DL-TFTs) using a quantum well channel and a top barrier can reduce the subthreshold swing and hysteresis by 0.73 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> and 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> , respectively, in the transfer characteristics using the bottom gate sweep as compared to the single-layer TFTs (SL-TFTs). The wide bandgap barrier on top of the narrow bandgap IGZO channel serves as a protection layer between the IGZO channel and the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> top gate insulator to prevent plasma-induced damage on the IGZO channel caused by the S/D metal etching and the top gate insulator deposition. As for the mobility using the bottom gate operation with the top gate grounded, the DL-TFTs show higher mobility (1.06 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> ) at the room temperature due to less Coulomb scattering caused by the plasma-induced damage for percolation conduction, while the SL-TFTs have higher mobility at low temperatures due to the improved hopping efficiency for thermally activated hopping. The hysteresis is temperature independent down to 160 K, indicating the electrons tunneling between the channel and the top gate insulator is dominant. As for the reliability, DL-TFT has a smaller V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift than SL-TFT under both positive bias temperature stress (PBTS) due to less subgap defect in the channel.

Highlights

Thin-film transistors (TFTs) with amorphous oxide semiconductor as the channel material have received much attention recently
The bandgap (Eg), valence band offsets (EF-EV, where EF is the Fermi level and EV is the valence band edge), and work function can be extracted by Tauc method [11], X-Ray photoelectron spectroscopy (XPS) [12], and Kelvin probe force microscopy (KPFM), respectively, to obtain the band alignment of HM and OF-STD IGZO (Fig. 2) [10]
Due to the same channel thickness and material of main channels for both double-layer Amorphous InGaZnO (a-IGZO) thin film transistors (DL-TFTs) and SLTFTs, and the small band bending in the top barrier of DL-TFTs, the carrier distributions in the channel are similar for both devices (Fig. 3)

Summary

INTRODUCTION

Thin-film transistors (TFTs) with amorphous oxide semiconductor as the channel material have received much attention recently. Amorphous InGaZnO (a-IGZO) is a promising channel material due to its low processing temperature, low leakage current, high uniformity, and high mobility. The etching stop layer (ESL) process can yield high performance and operation stability [6]–[9]. The backchannel-etch (BCE) process eliminates the etching stop layer patterning in the ESL process to reduce the number of masks with the penalty of plasma-induced damage during S/D metal etching and top gate insulator deposition. An additional top barrier is used to mitigate the damage of the back channel to improve the performance.

DEVICE FABRICATION

RESULTS AND DISCUSSION

CONCLUSION