65nm Technology Research Articles

A novel design of 1-bit full adders for eliminating voltage step in BBL-PT full adder using 32-nm CNTFET technology

ABSTRACT The full adder is essential for building computing systems like multipliers. Optimizing its design with CNTFET technology enhances low power, speed, and circuit density. This article presents a novel approach to address the challenges in Branch-Based Logic and Pass-Transistor (BBL-PT) based 1-bit full adder. The proposed approach involves the use of alternative modified level restorers, including a current sink, D-CNTFET (Diode connected CNTFET), modified current sink, and source structures. The BBL-PT full adder suffers from a voltage step issue in its output. The proposed solution eliminates this drawback using four alternative restorer structures. For +0.9 V supply voltage at 32-nm CNTFET technology, among all the proposed adder designs, the current sink based adder has a reported power consumption of 0.0845 μW, which is exceptionally low with the propagation delay is specified as 6.127 Ps and the Power-Delay Product (PDP) is 0.5177 aJ. The deliberate use of the current sink restorer in the design contributes to achieving these exceptional performance characteristics. An N-bit parallel adder (N=8, 16 & 32) using the proposed full adders is presented, with performance evaluated at 32-nm CNTFET technology and +0.9 V supply using Mentor Graphics tools. Results highlight its efficiency and superiority over existing solutions.

Optimized leakage control in CMOS NAND gates: the in-triggering technique

Abstract Leakage power, now the largest contributor to integrated circuit power consumption, is rising quickly, according to the International Technology Roadmap for Semiconductors (ITRS). As CMOS (complementary metal-oxide semiconductor) technology continues to shrink to deep submicron levels, gate leakage and subthreshold have become important components that contribute to total power dissipation. To address this problem, many methods have been put forth, especially at the circuit level. In 45 nm CMOS, variability and short-channel effects limit noise margins and compromise gate delays, thereby compromising the timing closure and robustness of ultra-low voltage circuits. The resulting supply voltage guardband may reduce energy efficiency in order to achieve a reasonable production yield. Furthermore, the high leakage currents of these technologies decrease energy efficiency when idle intervals are prolonged. In this study, two designs of a novel two-input NAND gate at 45 nm CMOS technology are constructed using eight transistors (8-T). A novel circuit technique named "In-Triggering (INDEP with Bi-Triggering)" is presented in this study with the goal of lowering subthreshold leakage in digital circuits. This method is thoroughly contrasted with other leakage reduction strategies now in use, such as Base, Sleepy LECTOR, LECTOR, INDEP, and Bi-Triggering procedures. Evaluation is done using key performance measures such power-delay product (PDP), latency, subthreshold leakage power, and total power consumption. 45-nm Predictive Technology Models (PTM) with a nominal supply voltage of 1V are used in the investigation. According to our findings, the suggested In-Triggering technique outperforms the conventional NAND gate in terms of speed by 12% and significantly reduces leakage power by up to 56%. Furthermore, compared to the Base, Trig01, and INDEP NAND gates, the method offers mean power savings of 58.8%, 36.1%, and 30.7%, respectively. At supply voltages of 1V, a comprehensive comparison and verification are then conducted utilizing the several proposed and existing methodologies. The effectiveness of the In-Triggering technique in reducing leakage power in CMOS circuits is confirmed by comparing these results to the most well-known design strategies for both active operation and sleep modes.

BP-IMCA: An Energy-Efficient 8T SRAM-Based Bit-Parallel In-Memory Computing Architecture

In-Memory Computing (IMC) is an emerging paradigm that aims to shift computational workload away from CPUs. The bit-serial IMC architecture suffers from larger latency when performing logic and arithmetic operations. In this paper, a general-purpose, energy-efficient Bit Parallel IMC Architecture (BP-IMCA) based on Area-Optimized (AO-8T) static random access memory (SRAM) bit-cell is proposed to perform In-Memory Boolean Logic Computation (IMBC) and Near-Memory Arithmetic (NMA) operations with variable bit-width from 1- to 8-bit. The decoupled read/write paths of the employed AO-8T SRAM bit-cell eliminate compute disturbance during IMBC and NMA operations. A self-terminating read word line decoding scheme is proposed to disconnect the RBL discharging path from GND, which decreases the energy consumption of the proposed IMC architecture by 27.71% at 1[Formula: see text]V for IMBC operations. In addition to this, a [Formula: see text]-based Low-offset Symmetric Differential Sense Amplifier (LSDSA) is proposed to achieve fast and reliable sensing for both normal read and IMBC operations in the proposed IMC architecture. Further, a 4[Formula: see text]Kb SRAM array is implemented in 65-nm technology to analyze the IMC architecture at a supply voltage of 1[Formula: see text]V. The operating frequency of 1,355[Formula: see text]MHz and average energy consumption of 7.04[Formula: see text]fJ/bit is achieved during logic (IMBC) operations. The 8-bit addition and 8-bit multiplication operations achieve an energy efficiency of 11.1 TOPS/W and 2.28 TOPS/W, respectively, at 1[Formula: see text]V and 970[Formula: see text]MHz. Cumulatively, the proposed architecture achieves the lowest figure of merit compared to the state-of-the-art IMC architectures.

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort

Hardware Trojans (HTs) are a longstanding threat to secure computation. Among different threat models, it is the fabrication-time insertion of additional malicious logic directly into the layout of integrated circuits (ICs) that constitutes the most versatile, yet challenging scenario, for both attackers and defenders.Here, we present a large-scale, first-of-its-kind community effort through red-versus-blue teaming that thoroughly explores this threat. Four independently competing blue teams of 23 IC designers in total had to analyze and fix vulnerabilities of representative IC layouts at the pre-silicon stage, whereas a red team of 3 experts in hardware security and IC design continuously pushed the boundaries of these defense efforts through different HTs and novel insertion techniques. Importantly, we find that, despite the blue teams’ commendable design efforts, even highly-optimized layouts retained at least some exploitable vulnerabilities.Our effort follows a real-world setting for a modern 7nm technology node and industrygrade tooling for IC design, all embedded into a fully-automated and extensible benchmarking framework. To ensure the relevance of this work, strict rules that adhere to real-world requirements for IC design and manufacturing were postulated by the organizers. For example, not a single violation for timing and design-rule checks were allowed for defense techniques. Besides, in an advancement over prior art, neither red nor blue teams were allowed to use any so-called fillers and spares for trivial attack or defense approaches.Finally, we release all methods and artifacts: the representative IC layouts and HTs, the devised attack and defense techniques, the evaluation metrics and setup, the technology setup and commercial-grade reference flow for IC design, the encompassing benchmarking framework, and all best results. This full release enables the community to continue exploring this important challenge for hardware security, in particular to focus on the urgent need for further advancements in defense strategies.

An Inversion-Coefficient Based Methodology for Optimizing the Performance of TIAs

ABSTRACT The transimpedance amplifier (TIA) can be found in several applications such as optical transceivers, biomedical circuits, and signal-processing circuits. In this paper, an investigation of two widely used transimpedance-amplifier configurations is presented. The two adopted configurations are the regulated cascode-based TIA (RGC-TIA) and the common-source based TIA (CS-TIA) with resistive feedback. These two configurations are studied in the following three inversion regimes; weak, moderate, and strong. A general model for the drain current of the MOSFET transistor, that is valid for all levels of inversion, is adopted. Through the study, the inversion coefficient (IC) of the amplifying device is systematically varied and its impact is investigated on various performance metrics such as gain, bandwidth, noise, distortion, and power consumption. Studying the inversion coefficient is crucial for precisely adjusting the amplifier biasing, thereby enabling the design of enhanced performance TIAs that effectively address the requirements of diverse applications. Compact-form expressions are derived for the performance metrics and compared with the simulation results. A figure of merit incorporating multiple performance metrics is proposed for performing a fair comparison for a wide range of the inversion coefficient. The simulation employs the 130-nm CMOS Predictive Technology Model (PTM) with a power-supply voltage, VDD , equal to 1.2 V.

An Energy-Efficient ECG Processor with Ultra-Low-Parameter Multi-Stage Neural Network and Optimized Power-of-Two Quantization.

This work presents an energy-efficient ECG processor designed for Cardiac Arrhythmia Classification. The processor integrates a pre-processing and neural network accelerator, achieved through algorithm-hardware co-design to optimize hardware resources. We propose a lightweight two-stage neural network architecture, where the first stage includes discrete wavelet transformation and an ultra-low-parameter multilayer perceptron (MLP) network, and the second stage utilizes group convolution and channel shuffle. Both stages leverage neural networks for hardware resource reuse and feature a reconfigurable processing element array and memory blocks adapted to the proposed two-stage structure to efficiently handle various convolution and MLP layers operations in the two-stage network. Additionally, an optimized power-of-two (OPOT) quantization technique is proposed to enhance accuracy in low-bit quantization, and a multiplier-less processing element structure tailored for the OPOT weight quantization is introduced. The ECG processor was implemented on a 65nm CMOS process technology with 4KB of SRAM memory, achieving an energy consumption per interference of 0.15 uJ with a power supply of 1V, 64% energy saving compared to the recent state-of-the-art work. Under 4-bit weight precision, the 5-class ECG signal classification accuracy reached 98.59% on the MIT-BIH arrhythmia dataset.

Design of CMOS low noise amplifier with inductive degeneration for navigation application

Abstract This paper presents an advanced Low Noise Amplifier (LNA) tailored for high-precision navigation applications, designed using the 180nm technology node and implemented in Cadence Virtuoso. The LNA features a single-ended amplifier configuration with cascaded NMOS transistors to achieve superior isolation and input matching through source degeneration, optimizing gain and noise performance. At 1.2 GHz, the amplifier achieves a gain of 33 dB and a noise figure of 1.3 dB. It demonstrates a 1 dB compression point of –16 dBm and a third-order intercept point (IIP3) of –10 dBm, with a power consumption of 44 mW from a 1.8 V supply. Post-layout simulations reflect a noise figure of 2.9 dB and a gain of 19.5 dB, highlighting practical design considerations. The layout area is 0.51 mm², underscoring the compact yet highly efficient design.

Investigation on Characteristics of in Situ Boron-Doped Sige Epitaxy below 600℃

Boron-doped SiGe is widely used as a source/drain (S/D) material in p-type metal-oxide–semiconductor field-effect transistors (FETs). With the advent of strain engineering in 90-nm node technology, selective epitaxial growth (SEG) with in situ doping has become a standard process for S/D material formation and continues to be employed in advanced architectures such as FinFETs and gate-all-around FETs. Traditionally, SiGe SEG processes have been conducted at temperatures above 600℃ [1]. However, the growing demand for low-temperature processes has led to increased interest in boron-doped SiGe epitaxy below 600℃. For example, to reduce S/D contact resistivity, highly doped SiGe epitaxy has been proposed in post-gate processes where low temperatures are crucial to prevent deformation of high-k oxide/metal gates [2]. Additionally, in monolithic complementary FETs—considered for sub 1-nm node logic device—low-temperature processing is required to minimize the thermal influence on the bottom FET during S/D formation for the top FET [3].This study investigates in situ boron-doped SiGe epitaxial layers grown in an ultra-high vacuum chemical vapor deposition system at temperatures below 600℃. The focus of this study is to understand the growth characteristics of films by analyzing how different growth conditions affect film properties. Secondary ion mass spectrometry was employed to measure the chemical concentrations of boron and germanium in the films. High-resolution X-ray diffractometry was used to calculate the lattice parameters of the boron-doped SiGe films, allowing determination of substitutional boron concentrations, which were then compared to chemical boron concentrations. In addition, atomic force microscopy was used to analyze the surface morphology of the films. These analyses provide a comprehensive investigation of the overall film properties and growth characteristics of boron-doped SiGe films grown at temperatures below 600℃. Acknowledgments This work was supported by the Technology Innovation Programs (RS-2023-00235609) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

Design of PNP SiGe HBTs Towards 200 GHz fmax

In the three decades of production, SiGe HBTs have numerous applications including RF and high-speed mixed-signal and analog. While successive generations of BiCMOS technologies in the past have employed process and layout scaling, the advanced high performance platforms (with several 100 GHz fmax) have mostly been restricted to SiGe NPN optimization, and the Si PNP is often only offered as a dependent device with significantly slower speed. There truly exists a gap in literature with the PNP device variants showcasing good fT and fmax above 150 GHz in a BiCMOS platform. It is worth noting that much of the serviceable applications above can be designed with NPN-only topologies. However, having the complementary PNP enables several advantages, including power savings, improved gain, reduced design complexity, and improved reliability.There are several challenges for making high performance PNP devices including reduced minority mobility in the intrinsic base from the conducting holes, elevated base current from minority electron injection into the emitter, and heterojunction barrier effect directly on the carrier pathway in the collector-base junction. The figure below shows the measured fT/fmax characteristics for a SiGe PNP with Ae = 0.12x2.5 um2 built using a 130nm technology framework optimized for a PNP-only process. The present work expands on the measured results (AC + DC) and the challenges faced in optimizing PNP performance for 200 GHz fmax and beyond. Figure 1

Challenges and Recommendations for Improving Blockchain-Based Bank Transfer Security in 5G IoT Applications

Blockchain technology in 5G IoT applications may improve security and efficiency. This paper examines blockchain-based bank transfer security problems and solutions for IoT applications. The security improvement framework we propose uses modern cryptographic algorithms and efficient consensus procedures for 5G-enabled IoT devices. Simulations show a 35% increase in transaction validation speed, from 2.3 seconds to 1.5 seconds. The framework also reduces energy usage per transaction by 42%, making it better for resource-constrained IoT devices. Bank transfer security indicators including fraud detection accuracy and data integrity increased 28% and 22%, respectively. A standardized threat simulation environment shows that the suggested architecture boosts DDoS resistance by 30%. Scalability, interoperability, and regulatory compliance remain issues despite these advances. This article suggests adaptive scaling algorithms, cross-platform integration solutions, and a compliance roadmap. The suggested methods seek to improve bank transfer security in 5G-enabled IoT environments and promote blockchain technology. It also raises awareness about vulnerabilities in IoT networks, including DDoS attacks and man-in-the-middle attacks, and the risks associated with reliance on third-party service providers. The study focuses on designing complete and adjustable protection for secure IoT and sensor networks, with the network layer sending digital information to the IoT system's server, the internet layer acting as a gateway between computers, and the application layer processing information displayed in the user interface. The paper investigates stealthy data exfiltration on IoT and presents a realistic assault approach and potential implementation strategy. The need for collaboration among enterprises, governments, and network operators is discussed, along with the need for standardized security standards, measures like end-to-end encryption and network segmentation, and education and awareness campaigns to address security concerns. The study explores the vulnerability of IoT devices to attacks, focusing on wireless protocols like Bluetooth and Zigbee. Researchers used two samples of smart light bulbs to analyze their light intensity, revealing that patterns can be seen in a single color at all times. Cross-domain attacks, such as clock mute and clock split attacks, are demonstrated using the I2C master-slave interface. The ADobf method, an obfuscated Trojan detection method, is introduced to mitigate clock attacks in I2C communication. Experimental results were evaluated using Verilog HDL and 45nm FreePDK technology. Finally, this work also explores the security risks posed by IoT devices in both civil and industrial applications, identifying protocol flaws and proposing solutions for analog-based hardware Trojans (HT) activity. The authors use Bluetooth low-energy protocols of smart bulbs to covertly exfiltrate data in conversationally secure air-gapped networks, using the GATT and General Access Profile layers of the protocol hierarchy to implement covert data channels and control the device.

Design Of A Phase-Locked Loop Using Current Starved Voltage Controlled Ring Oscillator In 45nm Technology

Design Of A Phase-Locked Loop Using Current Starved Voltage Controlled Ring Oscillator In 45nm Technology

Performance Analysis of 8x4 Barrel Shifters in CMOS and FINFET Technology

Shifters are essential components in digital circuits, enabling data manipulation and routing for a wide range of computational tasks. This study presents a comprehensive performance analysis of 8x4 barrel shifters implemented in two distinct semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. This study compares and evaluates the important parameters for these shifters at both technological nodes, such as power consumption. Additionally, we examine the effects of scaling on CMOS barrel shifters. Conversely, FinFET technology, recognized for overcoming certain limitations of CMOS, is assessed for its potential to enhance performance while preserving energy efficiency. Through detailed simulation and analysis, this study offers valuable insights into the benefits and limitations of CMOS and FinFET implementations for 8x4 barrel shifters. The circuit is implemented using Cadence Virtuoso and optimized to leverage the unique features and address the limitations of 45nm CMOS and 22nm FinFET technologies. Furthermore, the study offers recommendations for selecting the appropriate technology based on specific performance criteria and application needs. The findings aim to guide future design decisions and improvements in shifter technology.

Decoder and Multiplexer Comparison with Mixed Logic and CMOS Logic with 90nm Technology

Decoder and Multiplexer Comparison with Mixed Logic and CMOS Logic with 90nm Technology

The single event upset hardened design of spin transfer torque magnetic random access memory read circuits at 40 nm technology

With the advancement of technology nodes, the challenging space radiation environment poses a significant threat to memory reliability. Spin transfer torque magnetic random access memory (STT-MRAM) is a formidable candidate for non-volatile memory for space applications due to its advantages of non-volatility, durability, speed and compatibility with CMOS technology. Although the STT-MRAM memory unit magnetic tunnel junction (MTJ) is naturally immune to radiation effects, the single event upset (SEU) affects the peripheral circuitry. A radiation-hardened circuit is proposed, which theoretically does not have ‘0' upset nodes and automatically recovers from ‘1' upset. Moreover, the circuit's radiation-hardened performance was corroborated through hybrid simulation utilizing 40-nm technology. The findings of this investigation hold significance for the use of space radiation-hardened STT-MRAM.

Design of 8T DTMOS Schmitt Trigger SRAM Cell for IOT Applications

Abstract Internet of things (IoT) based systems require power-efficient circuits to raise the battery lifeline. This study presents a single-ended 8T SRAM cell. The core of the proposed 8T SRAM cell is composed of a Schmitt-Trigger circuit which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. Read operation of the proposed cell is conducted using the shared footer per word transistor. The write path is cut-off during the read operation, improving RSNM. A transmission gate placed in the cell core is used to cut the feedback path during write operation. To prove superiority of the proposed cell it is compared with four state-of-the-art SRAM cells under identical conditions on Cadence Virtuoso using 45nm technology at VDD=0.8 V. The proposed circuit shows a 135.74 % improvement in terms of RSNM and a 44.04 % improvement in terms of peak-to-peak power compared to the 6T DTMOS Cell.

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator

This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review

Background: Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits. Objectives: To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters. Findings: It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage. Novelty: The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. Keywords: Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

A Novel Sinusoidal Oscillator Using Single Voltage Differencing Buffered Amplifier

In this paper, a voltage differencing buffered amplifier (VDBA)-based second-order sinusoidal oscillator (SO) configuration, which provides voltage output at low impedance, is proposed. The circuit employs single VDBA, three resistors and two grounded capacitors, which presume its easy monolithic integration with preferred circuit simplicity. The nonidealities of VDBA due to parasitic and tracking errors are taken into consideration to study the nonideal behavior of proposed SO. Mathematical modeling of phase noise is computed in the paper. Active and passive sensitivities are calculated for the proposed configuration and are found to be less than unity rendering circuit insensitive to component variations followed by phase noise study. The functionality of the proposed topology is validated through cadence virtuoso ADE spectre tool at 180-nm technology node. Experimental verification is executed through commercially available ICs AD844 by good results. The total harmonic distortion (THD) is found to be below 3.5%. The observed frequency of oscillation is found to be in close agreement with the theoretical values. The PVT and Monte Carlo statistical analyses are also carried out to confirm the sensitivity of the proposed SO.

An exponential variation based PSO for analog circuit sizing in constrained environment

This work presents an Exponential Variation based Particle Swarm Optimization (EV-PSO) algorithm to improve the convergence rate and find an optimal solution to analog circuit optimization problems in a constrained-driven environment. Existing evolutionary algorithms have a lower convergence rate leading to higher design time. This work introduces two novel parameters, ζ1 and ζ2, into the velocity update equation. These parameters dynamically vary with the number of iterations. The algorithm was implemented on the Python platform. The results have shown that, in comparison to the considered existing methods, the exponential variation of the parameters ζ1 and ζ2 in the proposed algorithms have a larger rate of convergence. The proposed EV-PSO has a convergence rate of 27 iterations, which is 57.8%, 65.38%, and 59.1% better than the conventional PSO, differential evolution (DE) and genetic algorithm (GA) respectively. The typical design obtained from the optimal solution is verified through the simulation using 45-nm CMOS technology. The optimal solution presented in this work meets the desired input specifications within the specified constrained environment.

Structure and Principles of Operation of a Quaternion VLSI Multiplier

The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.