65nm CMOS Research Articles

Efficient 3’s Complement Circuit for Ternary-ALU

Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65[Formula: see text]nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

Ultra-wideband high gain low group delay variation amplifier for phased-array radar system

This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces a new notch for S11, thus extending the matching bandwidth. Staggered tuning of load impedance peaks at each stage facilitates a balance between flat gain and low group delay variation. The output stage further enhances the overall gain while reinforcing bandwidth and stability through resistive feedback, and employs an adaptive bias circuit for linearity improvement. Implemented in SMIC 40-nm CMOS technology, the proposed amplifier achieves good input impedance matching, flat gain and low group delay variation of ±73.5 ps over 4.7–16 GHz. The whole power consumption is 198.3 mW and the output 1 dB compression point (OP1dB) is greater than 9 dBm. After careful design, the chip size is 0.64 mm2.

A Dual-Band Dual-Polarized 2x2 Antenna Array with Beamforming for 5G AiP and mmWave Applications

In this study, we present a dual-band (28/39GHz) 2 by 2 antenna array design on a 10(4+2+4) multi-layer organic substrate with broad bandwidth and higher isolation onto a compact AiP module. In addition, the H-type slot antenna structure can improve interference and isolation between 28 and 39GHz bands. The measured result shows the isolation can larger than 15dB between low and high band. For antenna measurement, the spherical of probing chamber is utilized to validate 28/39GHz antenna pattern and performance with a package level passive testing. Our AiP measured result shows the return loss is better than 10 dB in 23.5-30.5 GHz range, with ~7 GHz bandwidth and provides a high-gain per element (above ~6 dBi) radiation pattern for 28GHz applications. For 39GHz band, the antenna has 7 GHz bandwidth and provides a 5 dBi gain between 38-45 GHz. Comparison of S-parameter between simulated and measured results, there is a good correlation to obtain the quality of manufacturing. Furthermore, a 28GHz beamforming array is designed and demonstrated. The beamfoming array consists of a four-channel transceiver with 2 x 2 antenna array. The beamformer IC is implemented by TSMC 90-nm CMOS technology and the flip-chip bonded on BT substrate. For beamforming test, an integrated socket and load board are designed for support the mmWave module and then connection between DUT and test system. The load board substrate includes the IF, LO, and DC distribution network for respectively. There are 4-channel transmit beamforming array front-end module for testing. Finally, the 3D beam steering of 2 by 2 antenna array is measured with multi-states at 28 GHz, with a maximum realized gain of 11.8 dBi achieved in the main beam (θ=0°). It shows that beamforming can be generated at a specific beam direction by controlling the phase of the signal in each antenna element.

A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS

A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS

A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS

A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators

This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, the 8.5–17.8-GHz output is covered and the phase noise is reduced by about 3 dB with the halving total equivalent inductance of the tank. Meanwhile, the clock distribution is designed to obtain 0.05–8.9-GHz output. By using the retiming and separate division techniques, frequency coupling is solved, and the implementation of the clock distribution is separated from its noise considerations, which alleviates design complexity. Fabricated in 65-nm CMOS process, the proposed CPPLL is verified, and it achieves −109.9-dBc/Hz@1 MHz phase noise and −71.6-dBc reference spur at 16-GHz output. The integrated jitter is 144 fs from 10 kHz to 100 MHz.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

Design and Implementation of CMOS and Transmission Gate Based Full Adder Using 45nm Technology

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied, and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Transmission gate based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Transmission gate based Full adder circuits. The entire circuit is simulated in Cadence Tools at 45nm CMOS process.

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications

Approximate computing is an innovative design methodology to reduce the design complexity with an improvement in power efficiency, performance and area by compromising on the requirement of accuracy. In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation to produce the final products are proposed. Two approximate Probability Based Booth Encoders (PBBE-1 and PBBE-2) have been proposed and used in the Booth multipliers. Error parameters have been measured and compared with the existing approximate booth multipliers. Exact booth multiplier of novel design existing in the literature has also been implemented for comparison purpose. The proposed approximate multipliers are then used in applications like image multiplication and IIR bi-quad filtering to prove their performance. Simulation results prove that the proposed booth multipliers outperform the existing approximate booth multipliers in terms of power and area with better accuracy. Synthesis results prove that the proposed Multiplier 6 was found to be the most efficient with a 56 % power consumption improvement and a 47 % area improvement when compared to the exact multiplier. All the simulations are carried out using Cadence® Genus with 180 nm CMOS process technology.

A metastable RNG using interleaved NAND- and NOR-based TEROs

ABSTRACT This study introduces a novel approach to address the limitations observed in existing random number generator (RNG) designs, focusing on the resolution for insufficiently covered problem statements and study purposes. In response to these challenges, we propose a high-throughput metastable-based RNG tailored for cryptography applications. Our design is featured with a two-layer transient effect ring oscillator (TERO) architecture, meticulously crafted to mitigate the locking phenomenon and enhance RNG randomness. Leveraging interleaved two-layer TEROs, realised through NAND and NOR SR latches, our RNG achieves unpredictable irregular sampling, crucial for cryptographic applications. To further enhance irregular sampling, the first layer of the RNG employs a multiplexer that selects inputs randomly. This multiplexer is governed by selection signals generated by the second layer of the RNG, ensuring superior randomness. Implemented using TSMC 40-nm CMOS process, our RNG passed the FIPS 140–1 randomness test at a clock frequency of 100 MHz, boasting a remarkable throughput of 50 Mbps. This study represents a significant advancement in RNG technology, addressing previous shortcomings and paving the way for high-speed communication systems’ secure cryptographic applications.

A CMOS Current Sensing Interface With Sub-pA DC Uncertainty

This paper presents a CMOS current sensing interface with a dedicated analysis on dc uncertainty, especially the relationship among averaging, standard deviation and Allan variance. The dependence of the Allan variance on various noise sources is analyzed. The noise leakage mechanisms due to circuit nonidealities that lead to dc uncertainty are presented. A general design strategy toward a low dc uncertainty is drawn in this work. An auto-zeroing (AZ) capacitive transimpedance amplifier (CTIA) is reported for near-zero signal loss and near-perfect noise cancelation to achieve a low dc uncertainty. A prototype design implemented on 180nm CMOS process is presented and the measurement result shows a 73fA dc uncertainty.

A Sub-1μW 16-Bit Fully Dynamic Zoom ADC Compatible With Free-Running and Incremental Modes Using Residue Feedforward and Extended Counting Techniques

This paper proposes a fully dynamic zoom ADC, which uses the residue feedforward technique to reduce the “fuzz” caused by the coarse SAR ADC’s quantization noise leakage in free running mode, and uses the extended counting technique to obtain the quantization error in incremental mode. The zoom ADC achieves high resolution in both modes. An improved cascoded floating-inverter-amplifier based integrator is used for low power and fully dynamic conversion. Fabricated in a standard 180nm CMOS process, the zoom ADC occupies an active area of 0.204mm, and consumes less than 1μW while achieving 102.1dB and 97.6dB SNDR in 95Hz bandwidth (BW) in free-running and incremental modes, respectively, corresponding to 182.2dB and 177.5dB FoMSNDR.

A 0.67 μV-IIRN super-T Ω-Z IN 17.5 μW/Ch Active Electrode With In-Channel Boosted CMRR for Distributed EEG Monitoring.

We present the design, development, and experimental characterization of an active electrode (AE) IC for wearable ambulatory EEG recording. The proposed architecture features in-AE double common-mode (CM) rejection, making the recording's CMRR independent of typically-significant AE-to-AE gain variations. Thanks to being DC coupled and needless of chopper stabilization for flicker noise suppression, the architecture yields a super-T Ω input impedance. Such a large input impedance makes the AE's CMRR practically immune to electrode-skin interface impedance variations across different recording channels, a critical feature for dry-electrode ambulatory systems. Signal quantization and serialization are also performed in-AE, which enables a distributed system in which all AEs use a single data bus for data/command communication to the backend module, thus significantly improving the system's scalability. Additionally, the presented AE hosts auxiliary modules for (i) detection of an unstable electrode-skin connection through continuous interface impedance monitoring, (ii) dynamic measurement and adjustment of input DC level, and (iii) a CM feedback loop for further CMRR enhancement. The article also presents the development of printed (extrusion) tattoo electrodes and their experimental characterization results with the proposed AE architecture. Besides bio-compatibility, low-cost, pattern flexibility, and quick fabrication process, the printed electrodes offer a very stable electrode-skin connection, conform to scalp shape, and exhibit consistent performance under various bending curvatures. Analog circuit blocks of the presented AE architecture are designed and fabricated using a standard 180 nm CMOS technology, and the [Formula: see text] IC is integrated with off-chip low-power digital modules on a PCB to form the AE. Our measurement results show a CMRR of 82.2 dB (at 60 Hz), amplification voltage gain of 52.8 dB, a bandwidth of 0.2-400 Hz, ±500 mV input DC offset tolerance, An input impedance [Formula: see text], and 0.67 μV RMS integrated input referred noise (0.5-100 Hz), while consuming 17.5 μW per channel. All auxiliary modules are tested experimentally, and the entire system is validated in-vivo, for both ECG and EEG recording.

Measurement Approach to Evaluation of Ultra-Low-Voltage Amplifier ASICs

Abstract This article presents measurement circuits and a test board developed for the experimental evaluation of prototype chip samples of the Fully Differential Difference Amplifier (FDDA). The Device Under Test (DUT) is an ultra low-voltage, high performance integrated FDDA designed and fabricated in 130nm CMOS technology. The power supply voltage of the FDDA is 400mV. The measurement circuits were implemented on the test board with the fabricated FDDA chip to evaluate its main parameters and properties. In this work, we focus on evaluation of the following parameters: the input offset voltage, the common-mode rejection ratio, and the power supply rejection ratio. The test board was developed and verified. The test board error was measured to be 38.73mV. The offset voltage of the FDDA was −0.66mV. The measured FDDA gain and gain bandwidth were 48dB and 550kHz, respectively. In addition to the measurement board, a graphical user interface was also developed to simplify the control of the device under test during measurements.

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.