10T Full Adder Research Articles

Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

32 bit Power, Area and delay efficient carry Select Adder Using modified 10T Full Adder

In VLSI design With the development in the technology, adder circuits and other all applications are concentrating on high speed and low power requirements. In many data processing CSLA is mainly used It is a faster adder. There is a scope for decreasing the power, area & increase in speed. In this paper, we proposed a system which is designed with CMOS modified 10T full adder. Here less number of transistors are utilized to design full adder. Cadence virtuoso tool is used in 90nm technology. This modified circuit works on pass transistor technology. 90nm technology with supply voltage 1.8V is used. It is designed using 2 inverters and pass transistors. We get full swing voltage at the output. So there is no degraded output for more number of inputs. In this newly designed full adder compare to existing 4T XNOR logic less number of transistors are used so area utilization and power is reduce.

Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

Ultra high speed full adder for biomedical applications

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic-in-Memory

Due to their CMOS compatibility, hafnium oxide based ferroelectric field-effect transistors (FeFET) gained remarkable attention recently, not only in the context of nonvolatile memory applications but also for being an auspicious candidate for novel combined memory and logic applications. In addition to bringing nonvolatility into existing logic circuits (Memory-in-Logic), FeFETs promise to guide the way to compact Logic-in-Memory solutions, where logic computations are examined in memory arrays or array-like structures. To increase the area-efficiency of such circuits, a dense integration of FeFETs and standard FETs is essential. In this paper, we show that the ultra-dense co-integration of FeFETs and nFETs (28nm HKMG) with shared active area does not alter the FeFET’s switching behavior, nor does it affect the baseline CMOS. Based on this, we propose the integration of a FeFET-based, 2-input look-up table (memory) directly into a 4-to-1 multiplexer (logic), which is utilized directly in a 2TNOR memory array or stand-alone circuit. The latter one dramatically reduces the transistor count by at least 33% compared to similar FeFET-based circuits. By storing values of the look-up table in a nonvolatile manner, no energy is consumed during standby mode, which enables normally-off computing. To take another step towards novel Logic-in-Memory designs, we experimentally demonstrate a very compact in-array 2T half adder and simulate an array-like 14T full adder, which exploit the advantages of the array arrangement: easy write procedure and a very compact, robust design. The proposed circuits exhibit energy-efficiency in the (sub)fJ-range and operation speeds of 1GHz.

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Design and Simulation of Low Power 10T Full Adder using Cadence 16nM Technology

Design and Simulation of Low Power 10T Full Adder using Cadence 16nM Technology

14T Full Adder in 125nm CMOS technology for FFT applications using piecewise constant interpolation f(x) = 2.0

14T Full Adder in 125nm CMOS technology for FFT applications using piecewise constant interpolation f(x) = 2.0

Design of 10T full adder cell for ultralow-power applications

Abstract This research paper performs symmetrical transient response analysis of FO4 inverter logic gate at 16-nm technology node. It is observed that symmetry is obtained at the aspect ratio (β) is equal to 3.52. With this β ratio, minimum energy point is investigated and found to be 0.15 V. At this minimum energy point, this research paper proposes an ultralow-power 10T 1-bit full adder circuit at 16-nm technology node in subthreshold region for energy constraint applications. It exhibits superior performance in terms of design metrics like propagation delay, average power, leakage power and energy at optimum supply voltage i.e., at 0.15 V. The proposed design achieves 1.81×, 3.39×, 2.25×, and 6.12× improvement in propagation delay, average power dissipation, leakage power dissipation and energy compared to conventional 1-bit full adder circuit. The proposed design exhibits 1.02× improvement in average power variability.

An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

MGDI based parallel adder for low power applications

The paper discusses a unique method to design low power circuits, which is called Gate Diffusion Input (GDI) method. Complex functions can be implemented using only two transistors by using this method. GDI technique allows for reduced power consumption, lower delay, lesser transistor count and decreased area of circuits. It also makes the system design less complex. Full adders and parallel adders, are major building blocks of different digital components like ALUs, DSPs etc. Hence, reducing power consumption of adders is very important. This work aims at building a parallel adder that consumes less power. A GDI based XOR gate is designed using which, a 10T full adder is designed which involves lesser number of devices compared to CMOS Full adder. The threshold loss in full adder is a major pitfall. A standard CMOS process compatible version of GDI cell, modified GDI, mGDI cell is proposed, using which a full adder is built. A 4-bit parallel adder is designed. The proposed technique consumes lesser area and has low power dissipation compared to CMOS design. Power consumption is reduced by 15% compared to CMOS design. Cadence tool at 180 nm is used to implement the designs.

One Bit 8T Full Adder Circuit Using 3T XOR Gate and One Multiplexer

One Bit 8T Full Adder Circuit Using 3T XOR Gate and One Multiplexer

Optimized CMOS Design of Full Adder using 45nm Technology

This paper presents low power full adder designed with pass transistor logic which reduces the area , power and delay. we compared conventional 28T CMOS full adder with 16T and 8T full adder in terms of area , power and delay using 45um Technology The schematic of all three design has been developed and its layout has been created using micro-wind tool. The result show that 8T full adder consumes 98% less power as conventional 28T& 65% less power compared to 16T full adder. Keywords Full adder, Pass Transistor logic(PTL), Transmission gate (TG) ,CMOS, Drive current, Channel Length.

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrade the performance of digital electronics circuit where adder is employed. This paper described a comparative analysis of double gate 10T and double gate 14T adder at 45nm technology. In this paper we calculate the leakage current, average power and Delay of the designed circuit of 10T and 14T Full adder. 10T double gate full adder achieves 31.25% reduction in active power and 95% reduction in leakage current as compared to 14T double gate full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45nm technology.

Analysis and optimization of Active Power and Delay of 10T Full Adder using Power Gating Technique at 45 nm Technology

An overview of performance analysis and comparison between various parameters of a low power high speed 10T full adder has been presented here. This paper shows comparative study of advancement over active power, leakage current and delay with power supply of (0.7v) .We have achieved reduction in active power consumption of 39.20 nW and propagation delay of 10.51 ns, which makes this circuit highly energy efficient and optimization can be achieved between power and delay. In this circuit we have reduced leakage current of 18.21 nA for power supply of 0.5v to 0.9v. Signification of these designs is substance by the simulation results obtained from cadence virtuoso tool at different technologies.

PMOS based 1-Bit Full Adder Cell

This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of power–delay product, temperature sustainability and noise immunity. It also shows remarkable improvement in threshold loss as compared to existing 8T full adder for certain input combinations. Therefore, the proposed design outperforms the existing adder and proves to be an optimal option for low power and energy efficient applications. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13.0.

Design of a novel low power 8-transistor 1-bit full adder cell

An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.