32-bit RISC Research Articles

Improving IIoT security: Unveiling threats through advanced side-channel analysis

The widespread deployment of IIoT edge devices makes them attractive victims for malicious activities. Consequently, how to implement trustworthy operations becomes a realistic topic in embedded systems. While most current physical systems for detecting malicious activities primarily focus on identifying known intrusion codes at the block level, they ignore that even an unnoticeable injected function can result in system-wide loss of security. In this paper, we propose a framework called CNDSW built on deep-learning side-channel analysis for function-level industrial control flow integrity monitoring. By collaboratively utilizing correlation analysis and deep-learning techniques, the dual window sliding monitoring mechanism in the proposed CNDSW framework demonstrates a real-time code intrusion tracking capacity on embedded controllers with a 99% detection accuracy on average. Instead of focusing on known block-level intrusions, we experimentally show that our model is feasible to detect function-level code intrusions without knowing the potential threat type. Besides, we further explore how different configurations of the CNDSW framework can help the monitoring process with different emphases and to which extent the model can concurrently detect multiple code intrusion activities. All our experiments are conducted on 32-bit ARM Cortex-M4 and 8-bit RISC MCUs across five different control flow programs, providing a comprehensive evaluation of the framework’s capabilities.

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Design and Implementation of RISC MIPS Processor on FPGA

Abstract: In this paper, the design and implementation of RISC Processor is proposed with MIPS (Microprocessor without interlocked pipelined stages) technique. This processor performs 16-bit operations using pipelined technique, to improve the performance. This processor performs arithmetic, logical and data movement operations, more efficiently in terms of delay and power. The processor is composed of five stages namely, instruction fetch, instruction decode, execute, memory access and write back. The proposed 16-bit RISC MIPS processor is designed using Verilog and validated using Modelism, it is synthesized using libraries of AMD 45nm technology in Xilinx tool and implemented on Xilinx Spartan 6 FPGA. The proposed RISC MIPS gives reduced overall delay of 3.565ns and overall power consumption of 0.014W.

Design and Implementation of High Speed and Area Optimized Vedic Processor for Embedded Systems

The proposed work on the design and implementation of a High-Speed and Area-Optimized Vedic Processor for Embedded Systems appears promising. Here's an outline that we might find useful for organizing our work. Discuss briefly the growing need for high-performance embedded systems and the crucial role of processors. Summarize prior research on Vedic Processors, highlighting major features and optimizations gained by earlier researchers. The exact Vedic mathematics ideas and sutras that we propose to exploit in our processor design. Detail tactics for obtaining high-speed operations in the CPU, taking into account parallelism, pipelining, and other optimization approaches. As the computational complexity of tiny battery-powered devices develops, this study addresses the need for a fast 16-bit RISC processor. The emphasis is on boosting processor capabilities by integrating a Multiply-Accumulator (MAC) unit based on Vedic mathematics. The inclusion of a new instruction set involves VHDL-based changes to the processor's architecture, to ensure simplicity and total compatibility with the current structure. This study describes an innovative strategy for enhancing the capabilities of modest 16-bit RISC processors by including a Vedic mathematics-based Multiply-Accumulator (MAC) unit. The objective is to improve processor functionality by providing a new instruction set, which will be performed through VHDL-based changes to the CPU's design. The newly designed instruction set keeps its structure basic, ensuring complete compatibility with the previous architecture. A 16-bit pipelined system based on Harvard design has several components in its pipeline, comprising register access, arithmetic execution, front-end logic execution, instruction fetch, and decode. The simulation results demonstrate the validity of the proposed design, demonstrating effective verification and synthesis of the MAC architecture on an FPGA platform.

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Design and Verification of LC3 Microcontroller

Abstract: The main focus of the work is on utilising System Verilog to verify and debug the LC-3 Microcontroller, a 16-bit RISC processor. The utilised LC-3 Design Under Test (DUT) contains numerous flaws in the Fetch, Decode, Execute, and Controller sub-design units as well as flaws throughout. Numerous intricate SV features, including OOPS, Randomization, Functional Coverage, Assertions, and UVM, are used to identify the problems. For testing and determining the origin of design problems, the System Verilog Hardware Verification Language is combined with the Mentor Graphics Questa Simulation Environment. As long as it adheres to the design standards, the LC-3 microcontroller used for verification is presumed to function flawlessly. Otherwise, any behaviour that is not in line with the design specifications is considered a bug. The paper offers an effective approach for Verification Engineers in the Embedded Systems Industry to use System Verilog, the newest trend in the EDA Industry today, as their preferred language for debugging.

The Renesas Automotive Story in the History of the Microprocessor

Renesas Electronics has a long history of providing high-quality and reliable microcontrollers to the automotive industry for many years. Renesas is the consolidation of the semiconductor units of Hitachi, Mitsubishi, and NEC Electronics. Hitachi and Mitsubishi's semiconductor businesses were divested from each company and merged into Renesas Technology in 2003. NEC Electronics’ semiconductor business was divested in 2010 and merged into a combined Renesas Electronics in 2010. Each company had developed various 8-bit and 16-bit complex instruction set computer (CISC) architecture devices and 32-bit RISC architecture devices. Elements of all these previous architectures' devices are found in the newest Renesas devices available today, with the 32-bit RH850 being the highest selling automotive microcontroller for several years since its introduction.

Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region

A method for runtime energy optimization based on the supply voltage (Vdd) and the threshold voltage (Vth) scaling is proposed. This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). The MEP dynamically fluctuates depending on the operating conditions determined by a target delay constraint, an activity factor and a chip temperature. In order to track the MEP, this paper proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold region down to the sub-threshold region. Based on the MEP determination formula, an MEP tracking algorithm is also proposed. The MEP tracking algorithm estimates the MEP even though the operating conditions widely change. Measurement results based on a 32-bit RISC processor fabricated in a 65-nm Silicon On Thin Buried oxide (SOTB) process technology show that the proposed method estimates the MEP within a 5% energy loss in comparison with the actual MEP operation.

RETRACTED: Design of english video learning platform based on FPGA system and sobel algorithm

In order to improve the system performance of image processing and improve the efficiency of image processing, we can use some hardware running image processing algorithms. in practice, we introduce some reconfigurable devices and more advanced programming languages to use FPGA for image processing. following will briefly introduce the design of FPGA in the edge detection system.The design has integrated a 32-bit soft RISC processor as dedicated hardware peripheral micro development and EDK embedded system developed by the system generator. Input is detected from a real-time image obtained from the CMOS camera displayed on the DVI display on the screen.

Enhancing network-on-chip performance by 32-bit RISC processor based on power and area efficiency

This papers deals with base design of the RISC-V 32b processor. It is used to support many additional commands including hardware loops, post-upgrade and save instructions and additional ALU instructions. RISC processors can be used in different ways, depending on speed and power consumption. Organized to design low power RISC processors through design and solution processes. The speed can also be increased by using the correct clock method. Decoding of execution, memory and rewriting. A one-sided clock signal is used for the middle stage. MIPS V adds a new data type, Single Associated (PS), which stores two single-point floating point numbers (32-bit) in a list of 64-bit floating point numbers. Existing floating point statement variants have been added for arithmetic operations, suitability and limitations to work with this type of data using the SIMD method. New instructions for downloading, transferring and transferring PS data have been added. This is the first command to skip the floating point SIMD with the available fonts.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

Low-cost, microcontroller-based, two-channel piezoelectric bender device for somatosensory experiments.

Understanding the joint encoding of multiple tactile stimulus features (e.g., spatial position, amplitude, and frequency of vibration) is a major goal of somatosensory neuroscience, and the development of experimental set-ups to probe joint encoding is important. We describe in detail a microcontroller-based, piezoelectric bender device for tactile experiments. The device comprises an Arduino Due microcontroller board with a 32-bit ARM Cortex-M3 RISC processor, and two 12-bit digital-to-analog converters, enabling precise, independent stimulation of adjacent epithelial points. Using laser doppler vibrometry, we developed a model of the benders' structural mechanics, which we implemented on the device. We used the device to delivered precise, reliable somatosensory stimulation in an experimental setting, recording electrophysiological responses in the peripheral nervous system of the Gisborne cockroach (Drymaplaneta semivitta) to sinusoidal vibration of tibial spines. We plotted tuning curves and derived bandwidths of multi-unit populations. We also stimulated rat facial vibrissae ex vivo. This microcontroller-based, low-cost, open-source system leverages a large developer community associated with Arduino, and may help speed advances in systems neuroscience.

Design and Implementation of Extended 16 Bit Co-Operative Arithmetic and Logic Unit (CALU) for 16 Bit Instructions

CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit, CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined system. Today in an era of 64 bit architectures, 8 bits are still very relevant and has not lost its position and being used in many applications. Hence this research work deals with 8 bit CPU architecture and its features enhancement to make the 8 bit case very relevant in an era of 64 bit. The co-operative ALU, as name suggests, works in tandem with existing ALU and performs 16 bits operations. The specially designed instructions shares knowledge and efficiently handles existing ALU and Co-operative ALU to perform 8 bits and 16 bits operations. The Co-operative ALU is integrated with the 2 stage pipelined 8-bit RISC architecture ensuring that existing architecture is kept intact by way of applying new functionality in the form of an extension. The reconfigurable platform software tools are used for functionality verification and final deployment is done using reconfigurable platform hardware tools.

Temporal Performance Analysis of Enhanced 8 Bit RISC Architecture

In this paper, we have proposed the development of the Enhanced 8-bit RISC architecture and the temporal performance analysis of the enhanced architecture. The enhanced 8 bit RISC architecture is powered with the additional block called as Co-operative Arithmetic and Logical Unit (CALU). The 8 bit core is designed using FPGA as SPARTAN-6 XC65LX9-3TQG144. The purpose of designing is to integrate number of instructions with additional instructions, which are 16 bits with keeping all original instructions execution having 8 bit format. We have designed the enhanced of 8 bit processor for improvement in speed as well as to speedup of the execution cycle, so that improvement in clock cycles per second for execution of an instruction. The Enhanced RISC architecture is fully compatible with the original core along with old instruction set. The CALU is designed to enhance the multi-byte capabilities of the core. The performance improvement in terms of the clock cycle savings has been recorded. The performance enhancement of average 71% has been recorded by the Enhanced core. The Enhanced RISC core has been developed and simulated on Xilinx Vivado 2017.3.

Total-ionization-dose characterization of a radiation-hardened mixed-signal microcontroller SoC in 180 nm CMOS technology for nanosatellites

This paper presents design techniques and measurement results of a radiation-hardened mixed-signal microcontroller system-on-chip (SoC) dedicated to fully-customized nanosatellites for the civil active space debris (ADR) cleaning missions. The design requirements are firstly given. The architecture of an on-board computer (OBC) is then described. A radiation-hardened-by-design (RHBD) SoC is proposed for such applications to obtain a long operational period. The proposed SoC is composed of a dual-modular redundant (DMR) 16-bit RISC processor, a 1 kB SRAM, a 12-bit pipelined SAR ADC, a 12-bit current-steering DAC and an on-chip clock generator. The radiation-hardened-by-design techniques are adopted to resist the total-ionization-dose (TID) effects. An SoC prototype is designed and fabricated in 180 nm CMOS process. The electronical performance of devices-under-test (DUTs) has been measured based on a customized mother-daughter board. The performance of the proposed SoC meet the requirements of the nanosatellites. Furthermore, the TID radiation effect experiment is performed. It indicated that the proposed SoC can resist the total dose of more than 300 krad (Si) at the dose rate of 50 rad (Si)/s.

Low Power Implementation of a RISC Machine Using Clock Gating Technique

In this work, 8bit RISC stored program machine is designed for low power by making use of clock gating technique. RISC stored program machine consists of different components namely memory unit, processing unit and control unit and these components are modelled by using Verilog HDL. The different sub modules of the RISC stored program machine are the processing unit, control unit and memory unit. Thereafter, power analysis of each of the different modules is done separately and consumption of power is observed. Same calculation of consumption of power is repeated by applying latch free and latch based clock gating techniques to the modules and the power consumption after applying clock gating is observed. And reduction in the power consumption of modules with clock gating is observed as 45% while analyzing using the Xpower tool of Xilinx ISE.

A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

Side-channel attacks are a prominent threat to the security of embedded systems. To perform them, an adversary evaluates the goodness of fit of a set of key-dependent power consumption models to a collection of side-channel measurements taken from an actual device, identifying the secret key value as the one yielding the best-fitting model. In this work, we analyze for the first time the microarchitectural components of a 32-bit in-order RISC CPU, showing which one of them is accountable for unexpected side-channel information leakage. We classify the leakage sources, identifying the data serialization points in the microarchitecture and providing a set of hints that can be fruitfully exploited to generate implementations resistant against side-channel attacks, either writing or generating proper assembly code.

8-bit softcore microprocessor with dual accumulator designed to be used in FPGA

Context: This paper is presents the design and implementation of an 8-bit softcore RISC microprocessor able to be run on space-optimized FPGA, in order to be used for embedded applications.Method: The design of this microprocessor was developed in Verilog hardware description language and can be implemented in FPGA from different manufacturers; therefore, the user has only to define the input and output ports according to the type of FPGA. This is an accumulator-type processor, but it has two different accumulators that can be used as pointers for indirect addressing. The processor is Harvard with a RAM of 8x256 bits, and a ROM that can be resized from 17x252 bits to 17x8K bits. Additionally, it has one 8-bit input port, one 8-bit output port, and one 8-bit address port, which means that the processor can address more than 256 8-bit output ports/devices. The same applies for input ports.Results: The developed processor, named “ZA-SUA,” was compared with PICOBLAZE softcore and other three similar processors of free distribution in the Web, and some improvements over those were found. Criteria such as the Flip Flops used, occupied LUTs, Slices in use, and maximum delay of each processor were analyzed, all these results were obtained from the implementation of the processors in the Xilinx FPGAs.Conclusions: The designed architecture is composed by two accumulators, which can be used either as source or destination for the operation of the ALU. This fact gives some flexibility to the design, doing it better than a single-accumulator processor, and getting it closer to the register-based processors.

Pipeline Hazards Resolution for a New Programmable Instruction Set RISC Processor

The work presented in this paper is a part of a project that aims to concept and implement a hardwired programmable processor. A 32-bit RISC processor with customizable ALU (Arithmetic and Logic Unit) is designed then the pipeline technique is implemented is order to reach better performances. However the use of this technique can lead to several troubles called hazards that can affect the correct execution of the program. In this context, this paper identifies and analyzes all different hazards that can occur in this processor pipeline stages. Then detailed solutions are proposed, implemented and validated.

Implementation of an 8-Bit Softcore Microcontroller on Xilinx Spartan FPGA Family

Objectives: To design an 8-bit RISC microcontroller in VHDL and implement it on an FPGA, taking as a reference the mid-range microcontroller core of Microchip 16FXXX. Methods/Analysis: This microcontroller has been designed using modular blocks and correspond Harvard-type architecture. It has a stack of eight levels and an Arithmetic Logic Unit (ALU) for operations with 8-bit data and bit-oriented instructions. Also, it has a program memory of 8Kx14-bit and a data memory of 512x8-bit. The number of storage locations of these memory modules is easily scalable and/or modified as needed by the designer due to high abstraction level which has been used in its description. Similarly, the other blocks (as well as the microcontroller in general) are easily modified, providing a modular system resulting in excellent versatility to be adapted to be additional modules including: input and output ports, timers, blocks for communication among others. Findings: The proposed device has an instruction OPCODE correspondent to PIC16FXX processor core, so the system can be programmed with the same machine language. It also presents a high support for compilers such as MPASM (Microchip Assembler) and CCS PIC-C (C language). The compatibility with the C compiler is quite interesting, making easy the development of large-scale digital designs, thanks to the existence of extensive libraries in this programming language. Novelty/ Improvements: The system provides the enough user support. A document was generated with all data and instructions that the designer needs to take into account for executing or modifying the microcontroller design. This support, along with the open source firmware, was published on the Internet, so that communities can access it, adopt it and/or modify it.