Bits Of Precision Research Articles

Quantized neural network for complex hologram generation

Computer-generated holography (CGH) is a promising technology for augmented reality displays, such as head-mounted or head-up displays. However, its high computational demand makes it impractical for implementation. Recent efforts to integrate neural networks into CGH have successfully accelerated computing speed, demonstrating the potential to overcome the trade-off between computational cost and image quality. Nevertheless, deploying neural-network-based CGH algorithms on computationally limited embedded systems requires more efficient models with lower computational cost, memory footprint, and power consumption. In this study, we developed a lightweight model for complex hologram generation by introducing neural network quantization. Specifically, we built a model based on tensor holography and quantized it from 32-bit floating-point precision (FP32) to 8-bit integer precision (INT8). Our performance evaluation shows that the proposed INT8 model achieves hologram quality comparable to that of the FP32 model while reducing the model size by approximately 70% and increasing the speed fourfold. Additionally, we implemented the INT8 model on a system-on-module to demonstrate its deployability on embedded platforms and high power efficiency.

Direct Current to Digital Converter (DIDC): A Current Sensor.

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field.

High-resolution in vivo 4D-OCT fish-eye imaging using 3D-UNet with multi-level residue decoder.

Optical coherence tomography (OCT) allows high-resolution volumetric imaging of biological tissues in vivo. However, 3D-image acquisition often suffers from motion artifacts due to slow frame rates and involuntary and physiological movements of living tissue. To solve these issues, we implement a real-time 4D-OCT system capable of reconstructing near-distortion-free volumetric images based on a deep learning-based reconstruction algorithm. The system initially collects undersampled volumetric images at a high speed and then upsamples the images in real-time by a convolutional neural network (CNN) that generates high-frequency features using a deep learning algorithm. We compare and analyze both dual-2D- and 3D-UNet-based networks for the OCT 3D high-resolution image reconstruction. We refine the network architecture by incorporating multi-level information to accelerate convergence and improve accuracy. The network is optimized by utilizing the 16-bit floating-point precision for network parameters to conserve GPU memory and enhance efficiency. The result shows that the refined and optimized 3D-network is capable of retrieving the tissue structure more precisely and enable real-time 4D-OCT imaging at a rate greater than 10 Hz with a root mean square error (RMSE) of ∼0.03.

Eye-Net: A Low-Complexity Distributed Denial of Service Attack-Detection System Based on Multilayer Perceptron

Distributed Denial of Service (DDoS) attacks disrupt service availability, leading to significant financial setbacks for individuals and businesses. This paper introduces Eye-Net, a deep learning-based system optimized for DDoS attack detection that combines feature selection, balancing methods, Multilayer Perceptron (MLP), and quantization-aware training (QAT) techniques. An Analysis of Variance (ANOVA) algorithm is initially applied to the dataset to identify the most distinctive features. Subsequently, the Synthetic Minority Oversampling Technique (SMOTE) balances the dataset by augmenting samples for under-represented classes. Two distinct MLP models are developed: one for the binary classification of flow packets as regular or DDoS traffic and another for identifying six specific DDoS attack types. We store MLP model weights at 8-bit precision by incorporating the quantization-aware training technique. This adjustment slashes memory use by a factor of four and reduces computational cost similarly, making Eye-Net suitable for Internet of Things (IoT) devices. Both models are rigorously trained and assessed using the CICDDoS2019 dataset. Test results reveal that Eye-Net excels, surpassing contemporary DDoS detection techniques in accuracy, recall, precision, and F1 Score. The multiclass model achieves an impressive accuracy of 96.47% with an error rate of 8.78%, while the binary model showcases an outstanding 99.99% accuracy, maintaining a negligible error rate of 0.02%.

Deep learning and quantization for accurate and efficient multi-target radar inference of moving targets

Real-time, radar-based human activity and target classification is useful for wide-area ground surveillance. However, the feasibility of deploying deep learning (DL) models in radar-based systems with limited computational resources remains unexplored. This paper investigated the effect of quantization on model throughput and accuracy for deployment in radar systems. A seven-layer residual network was proposed to classify ground-moving targets and achieved a test accuracy of 87.72%. The model was then quantized to 16-bit and 8-bit precision, resulting in a 3.8 times speedup in inference throughput, with less than a 0.4% drop in test and validation accuracy. The results showed that quantization can improve inference throughput with a negligible decrease in target classification accuracy. The increase in throughput and reduction in computational expense that comes with quantization promotes the feasibility of the deployment of DL models in systems with limited computational resources. The findings of this paper hold significant promise for the successful use of quantized models in modern radar systems, while adhering to stringent size, weight and power consumption constraints.

Compression of Medical images using SPIHT Algorithm for Telemedicine Application

Image compression plays a pivotal role in the medical field for the storage and transfer of DICOM images. This research work focuses on the compression of medical images using Set Partitioning in Hierarchy Trees (SPIHT) algorithm. The CT/MR images are used as input, the images are subjected to filtering by a median filter. The CT images in general are corrupted by Gaussian noise and MR images are corrupted by rician noise. The SPIHT algorithm comprises of following phases; transformation into wavelet domain, refinement pass and sorting pass. The Haar wavelet transform is employed and the wavelet coefficients are subjected to sorting and refinement pass. The Haar wavelet transform generates LL, HL, HL and HH sub-bands. In the sorting pass, the coefficients are classified into significant and insignificant. The refinement pass creates the precision bits for the significant coefficients. The main characteristic of the SPIHT algorithm is that it does not use an entropy coder. The reconstructed image in the decoding stage was validated by performance metrics. The SPIHT algorithm generates proficient results, when compared with the classical algorithms like wavelet and embedded zero tree wavelet (EZW) algorithms.

FPGA-based Lightweight QDS-CNN System for sEMG Gesture and Force Level Recognition.

Deep learning (DL) has been used for electromyographic (EMG) signal recognition and achieved high accuracy for multiple classification tasks. However, implementation in resource-constrained prostheses and human-computer interaction devices remains challenging. To overcome these problems, this paper implemented a low-power system for EMG gesture and force level recognition using Zynq architecture. Firstly, a lightweight network model structure was proposed by Ultra-lightweight depth separable convolution (UL-DSC) and channel attention-global average pooling (CA-GAP) to reduce the computational complexity while maintaining accuracy. A wearable EMG acquisition device for real-time data acquisition was subsequently developed with size of 36mm×28mm×4mm. Finally, a highly parallelized dedicated hardware accelerator architecture was designed for inference computation. 18 gestures were tested, including force levels from 22 healthy subjects. The results indicate that the average accuracy rate was 94.92% for a model with 5.0k parameters and a size of 0.026MB. Specifically, the average recognition accuracy for static and force-level gestures was 98.47% and 89.92%, respectively. The proposed hardware accelerator architecture was deployed with 8-bit precision, a single-frame signal inference time of 41.9μs, a power consumption of 0.317W, and a data throughput of 78.6 GOP/s.

Quantum algorithm for ground state energy estimation using circuit depth with exponentially improved dependence on precision

A milestone in the field of quantum computing will be solving problems in quantum chemistry and materials faster than state-of-the-art classical methods. The current understanding is that achieving quantum advantage in this area will require some degree of fault tolerance. While hardware is improving towards this milestone, optimizing quantum algorithms also brings it closer to the present. Existing methods for ground state energy estimation are costly in that they require a number of gates per circuit that grows exponentially with the desired number of bits in precision. We reduce this cost exponentially, by developing a ground state energy estimation algorithm for which this cost grows linearly in the number of bits of precision. Relative to recent resource estimates of ground state energy estimation for the industrially-relevant molecules of ethylene-carbonate and PF6−, the estimated gate count and circuit depth is reduced by a factor of 43 and 78, respectively. Furthermore, the algorithm can use additional circuit depth to reduce the total runtime. These features make our algorithm a promising candidate for realizing quantum advantage in the era of early fault-tolerant quantum computing.

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET

Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35–133 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.

ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization.

Recently, the efficient training of deep neural networks (DNNs) on resource-constrained platforms has attracted increasing attention for protecting user privacy. However, it is still a severe challenge since the DNN training involves intensive computations and a large amount of data access. To deal with these issues, in this work, we implement an efficient training accelerator (ETA) on field-programmable gate array (FPGA) by adopting a hardware-algorithm co-optimization approach. A novel training scheme is proposed to effectively train DNNs using 8-bit precision with arbitrary batch sizes, in which a compact but powerful data format and a hardware-oriented normalization layer are introduced. Thus the computational complexity and memory accesses are significantly reduced. In the ETA, a reconfigurable processing element (PE) is designed to support various computational patterns during training while avoiding redundant calculations from nonunit-stride convolutional layers. With a flexible network-on-chip (NoC) and a hierarchical PE array, computational parallelism and data reuse can be fully exploited, and memory accesses are further reduced. In addition, a unified computing core is developed to execute auxiliary layers such as normalization and weight update (WU), which works in a time-multiplexed manner and consumes only a small amount of hardware resources. The experiments show that our training scheme achieves the state-of-the-art accuracy across multiple models, including CIFAR-VGG16, CIFAR-ResNet20, CIFAR-InceptionV3, ResNet18, and ResNet50. Evaluated on three networks (CIFAR-VGG16, CIFAR-ResNet20, and ResNet18), our ETA on Xilinx VC709 FPGA achieves 610.98, 658.64, and 811.24 GOPS in terms of throughput, respectively. Compared with the prior art, our design demonstrates a speedup of 3.65x and an energy efficiency improvement of 8.54x on CIFAR-ResNet20.

Funshade: Function Secret Sharing for Two-Party Secure Thresholded Distance Evaluation

We propose a novel privacy-preserving, two-party computation of various distance metrics (e.g., Hamming distance, Scalar Product) followed by a comparison with a fixed threshold, which is known as one of the most useful and popular building blocks for many different applications including machine learning, biometric matching, etc. Our solution builds upon recent advances in function secret sharing and makes use of an optimized version of arithmetic secret sharing. Thanks to this combination, our new solution named Funshade is the first to require only one round of communication and two ring elements of communication in the online phase, outperforming all prior state-of-the-art schemes while relying on lightweight cryptographic primitives. Lastly, we implement our solution from scratch in portable C and expose it in Python, testifying its high performance by running secure biometric identification against a database of 1 million records in ~10 seconds with full correctness and 32-bit precision, without parallelization.

An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros.

This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 μs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 μW with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.

Adaptive STDP-based on-chip spike pattern detection.

A spiking neural network (SNN) is a bottom-up tool used to describe information processing in brain microcircuits. It is becoming a crucial neuromorphic computational model. Spike-timing-dependent plasticity (STDP) is an unsupervised brain-like learning rule implemented in many SNNs and neuromorphic chips. However, a significant performance gap exists between ideal model simulation and neuromorphic implementation. The performance of STDP learning in neuromorphic chips deteriorates because the resolution of synaptic efficacy in such chips is generally restricted to 6 bits or less, whereas simulations employ the entire 64-bit floating-point precision available on digital computers. Previously, we introduced a bio-inspired learning rule named adaptive STDP and demonstrated via numerical simulation that adaptive STDP (using only 4-bit fixed-point synaptic efficacy) performs similarly to STDP learning (using 64-bit floating-point precision) in a noisy spike pattern detection model. Herein, we present the experimental results demonstrating the performance of adaptive STDP learning. To the best of our knowledge, this is the first study that demonstrates unsupervised noisy spatiotemporal spike pattern detection to perform well and maintain the simulation performance on a mixed-signal CMOS neuromorphic chip with low-resolution synaptic efficacy. The chip was designed in Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS technology node and comprises a soma circuit and 256 synapse circuits along with their learning circuitry.

Using copies can improve precision in continuous-time quantum computing

In the quantum optimisation setting, we build on a scheme introduced by Young et al (2013 Phys. Rev. A 88 062314), where physical qubits in multiple copies of a problem encoded into an Ising spin Hamiltonian are linked together to increase the logical system’s robustness to error. We introduce several innovations that improve the error suppression of this scheme under a special model of control noise, designed to understand how limited precision could be overcome. First, we note that only one copy needs to be correct by the end of the computation, since solution quality can be checked efficiently. Second, we find that ferromagnetic links do not generally help in this ‘one correct copy’ setting, but anti-ferromagnetic links do help on average, by suppressing the chance of the same error being present on all of the copies. Third, we find that minimum-strength anti-ferromagnetic links perform best, by counteracting the spin-flips induced by the errors. We have numerically tested our innovations on small instances of spin glasses from Callison et al (2019 New J. Phys. 21 123022), and we find improved error tolerance for three or more copies in configurations that include frustration. Interpreted as an effective precision increase, we obtain several extra bits of precision on average for three copies connected in a triangle. This provides proof-of-concept of a method for scaling quantum annealing beyond the precision limits of hardware, a step towards fault tolerance in this setting.

Parallel Matrix Multiplication Using Voltage-Controlled Magnetic Anisotropy Domain Wall Logic

The domain wall-magnetic tunnel junction (DW-MTJ) is a versatile device that can simultaneously store data and perform computations. These three-terminal devices are promising for digital logic due to their nonvolatility, low-energy operation, and radiation hardness. Here, we augment the DW-MTJ logic gate with voltage controlled magnetic anisotropy (VCMA) to improve the reliability of logical concatenation in the presence of realistic process variations. VCMA creates potential wells that allow for reliable and repeatable localization of domain walls. The DW-MTJ logic gate supports different fanouts, allowing for multiple inputs and outputs for a single device without affecting area. We simulate a systolic array of DW-MTJ Multiply-Accumulate (MAC) with 4-bit and 8-bit precision, which uses the nonvolatility of DW-MTJ logic gates to enable fine-grained pipelining and high parallelism. The DW-MTJ systolic array provides comparable throughput and efficiency to state-of-the-art CMOS systolic arrays while being radiation-hard. These results improve the feasibility of using domain wall-based processors, especially for extreme-environment applications such as space.

A Data Integrity Authentication Scheme in WSNs Based on Double Watermark

Aiming at data security in Wireless Sensor Networks (WSNs), a data authentication scheme based on double watermark is proposed in this paper. Double watermark includes reversible watermark and irreversible watermark. The former generated by group head data is embedded into the effective precision bit of data, and the latter generated by the effective precision bit of the data themselves and a defined array is embedded into the flag bit in two cases. Two adjacent groups form a working group. For the first case, a flag-check matrix is constructed by the special data set which includes the head of the current group and the tail of the previous group, and the data around them. Through the matrix, the watermark is embedded into the special data set to ensure the robustness of grouping. For the second case, watermark is embedded into the group data except special data set (the rest data) to ensure efficient detection of attacks. When the attacked position and type are detected, the data that are not tampered with in this group can still recover the effective precision bit. The security analysis and experimental results demonstrate that the comprehensive performance of the proposed scheme outperforms that of those state-of-the-art schemes.

X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units

This paper investigates a runtime accuracy reconfigurable implementation of an energy efficient deep learning accelerator. It is based on voltage overscaling (VOS) technique which provides dynamic adjustment of approximation level as well as improving lifetime/reliability of the accelerator. The technique is applied to both computing and memory units where based on the minimum required accuracy, the applied voltage is adjusted during the runtime. The implementation of the network is performed using NVDLA which is an open-source CNN (Convolutional Neural Network) accelerator. The approximation is applied to both the accelerator MAC array employed for the required network computations and to the accelerator SRAM memory utilized for storing the inputs (images), weights, and activation data. To control the accuracy degradation of the approximate accelerator (called X-NVDLA), the reduced voltage is applied only to LSB bits of the MAC array and SRAM unit. To assess the efficacy of the proposed energy efficient accelerator, the energy-accuracy characteristics of X-NVDLA when running LeNet-5 and ResNet-50 networks with 8-bit (integer) precision are investigated. In addition, the characteristic of bias temperature instability (BTI), as one of the lifetime deteriorating phenomena is determined. The study includes energy improvement versus accuracy degradation as a function of overscaled voltages and number of approximate the least significant bits using a 15nm FinFET technology.

An exponential function accelerator with radix-16 algorithm for spiking neural networks

A range reduction method for shift-and-add algorithms for exponential functions is proposed in this paper. An exponential function accelerator with this method and radix-16 shift-and-add algorithm has been implemented in SMIC 55 nm CMOS process. Compared with the existing method, the proposed method reduces the latency (cycles) by 33% and 20% for 16 and 32-bit precision results, respectively; thereby increasing the throughput to 50M exp/s and reducing the power consumption to 4.6 pJ/exp. In addition, this method saves die area since no arithmetic units are adopted. This exponential accelerator is supposed to be used in a neuromorphic chip for spiking neural network modeling.

An Instruction-Driven Batch-Based High-Performance Resource-Efficient LSTM Accelerator on FPGA

In recent years, long short-term memory (LSTM) has been used in many speech recognition tasks, due to its excellent performance. Due to a large amount of calculation and complex data dependencies of LSTM, it is often not so efficient to deploy on the field-programmable gate array (FPGA) platform. This paper proposes an LSTM accelerator, driven by a specific instruction set. The accelerator consists of a matrix multiplication unit and a post-processing unit. The matrix multiplication unit uses staggered timing of read data to reduce register usage. The post-processing unit can complete various calculations with only a small amount of digital signal processing (DSP) slices, through resource sharing, and at the same time, the memory footprint is reduced, through the well-designed data flow design. The accelerator is batch-based and capable of computing data from multiple users simultaneously. Since the calculation process of LSTM is divided into a sequence of instructions, it is feasible to execute multi-layer LSTM networks as well as large-scale LSTM networks. Experimental results show that our accelerator can achieve a performance of 2036 GOPS at 16-bit data precision, while having higher hardware utilization compared to previous work.

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

Compute-in-memory (CiM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, the tradeoff between energy efficiency and computing precision plagues most CiM implementations, and the low precision imposes a major limitation on CiM’s ability to support practical computational workloads. In this article, a static random access memory (SRAM)-based analog CiM macro is presented with the Intel 22FFL process. By introducing a 1-to-2 ratioed capacitor ladder (C-2C)-based charge domain computing scheme, the proposed CiM prototype chip demonstrates a maximum of 2k multiply-accumulate (MAC) operations in one clock cycle and achieves 32.2-TOPS/W peak power efficiency with 8-bit precision in both input activation and weight while ensuring accurate on-chip matrix–vector multiplications (MVMs) with a computation error less than 0.5%. A 4.0-TOPS/mm2 peak area efficiency is attained by adopting a local weight multiplexing scheme with a 9T SRAM cell, which improves the memory density and reduces the need to refresh the weight stored in the SRAM array. A variety of analog impairment factors, including parasitics, mismatch, and noise, were analyzed to guarantee a sufficiently high multibit linearity. The proposed passive analog computing mechanism ensures the computation accuracy over process–voltage–temperature (PVT), with the measured MVM error deviation of less than 1% over PVT variations.