Abstract
A range reduction method for shift-and-add algorithms for exponential functions is proposed in this paper. An exponential function accelerator with this method and radix-16 shift-and-add algorithm has been implemented in SMIC 55 nm CMOS process. Compared with the existing method, the proposed method reduces the latency (cycles) by 33% and 20% for 16 and 32-bit precision results, respectively; thereby increasing the throughput to 50M exp/s and reducing the power consumption to 4.6 pJ/exp. In addition, this method saves die area since no arithmetic units are adopted. This exponential accelerator is supposed to be used in a neuromorphic chip for spiking neural network modeling.
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