6T SRAM Circuits Research Articles

Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${f}_{\text {max}}$ </tex-math></inline-formula> IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on&#x2013;off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula>). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

Impact of uniform and non-uniform doping variations for ultrathin body junctionless FinFETs

In this paper, 3-D device simulations are performed to analyze the variations of uniform and non-uniformly (Gaussian) doped junctionless FinFETs. The impact of Fin width (Fw), Fin height (Fh), Channel length (Lg) and Gate Oxide (tox) on drain current, ION/IOFF ratio, subthreshold swing, Drain Induced Barrier Lowering (DIBL) of Si based Bulk Junctionless FinFETs is investigated. The results shows that the ION = 183μA/μm, IOFF = 4.449 × 10−5 μA/μm, is achieved for non-uniformly doping when compared to uniform doping configurations with ION = 102 μA/μm, IOFF = 3.05 × 10−5 μA/μm of junctionless FinFETs. Furthermore, the results also shows that non-uniformly doped junctionless FinFETs with fin width of 6 nm exhibits better DIBL of 22.5 mV/V and Subthreshold swing of 62.04 mV/decade than the uniform doped junctionless FinFET with DIBL of 80 mv/V and Subthreshold swing of 67.62 mV/decade. Thus, the non-uniformly doped junctionless FinFETs can effectively improve the performance of Junctionless FinFETs. In addition, to reduce the leakage current in bulk FinFETs effect of Punch-through Stop (PTS) layer, bulk doping concentration and body bias variations are studied. Finally, the 6T-SRAM circuit was implemented for JL-FinFETs and the results suggest that Gaussian doping JL-FinFETs strengthens the applicability of SRAM in the memory design.

Circuit performance analysis of graded doping of channel of DGMOS with high‐k gate stack for analogue and digital application

Double-gate MOSFET with graded channel doping is studied in this work, where the source and drain ends of the channel are doped with different concentrations to yield two different versions of the above device namely high-low (HL) and low-high (LH). The digital and analogue performances of these devices are investigated, respectively, by implementing 6T SRAM circuit and differential amplifier using the proposed device. Along with the doping variation, a high-K gate stack is also considered for only N type device to observe the effects of the proposed device on its circuit performance. The effective oxide thickness ( EOT ) of p type device is kept constant at 1.5 nm for all the circuit analysis. Hafnium oxide (HfO2) is used as high-K oxide along with silicon-di-oxide (SiO2) to maintain the required EOT of the device. Performance study shows that HL devices are best suited for digital application, whereas its counterpart LH devices perform better in analogue domain.

Topological variation on sub-20 nm double-gate inversion and Junctionless-FinFET based 6T-SRAM circuits and its SEU radiation performance

Introduction of new conduction mechanism called junctionless in MOSFETs takes us to another direction in device fabrication. Moving from inversion to junctionless devices in nanoscale regime proves a good alternative for low-power applications and overcomes the barrier of lightly doped channels. 6T-SRAM circuits, the first to arrive in the market long ago, still occupy its area in modern-day ICs too. In this work, four topologies of 6T-SRAM namely Flex-Vth, Flex-PG, PG-SN, and FinFETs are generated based on inversion type independent double-gate as well as common double-gate devices. For the first time, the same four topologies are also generated using junctionless devices. In nanoscale range, the reliability of circuits is given paramount importance since they are easily affected by radiation. This 6T-SRAM's radiation sensitivity is studied and from our simulation results, the common double-gate based 6T-SRAM shows good performance over the independent double-gate based 6T-SRAM in both inversion and junctionless type.

Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation

Scaling of metal---oxide---semiconductor field-effect transistors (MOSFETs) to below a few tens of nanometer has failed to make significant improvements. FinFETs were introduced to replace MOS devices in circuits, offering good performance improvement in the nanoscale regime. Memories occupy a major portion of chip area. Their reliability is a primary concern in harsh environments such as cosmic radiation. Also, in the nanoscale regime, reliability proves to be challenging. We present herein FinFET- and junctionless FinFET-based 6T-static random-access memories (SRAMs) for the 16-nm technology node. In the literature so far, either drain or gate strike has been considered. In this work, we studied irradiation in both the drain and the gate region. The FinFET-based 6T-SRAM showed higher hardness to single-event upset (SEU) radiation in both regions compared to junctionless FinFET-based 6T-SRAM.

Novel 8T Bit-cell with High RSNM for Sub-threshold SRAM

Since the sub-threshold circuit technology was widely applied to SRAM circuit, the power supply voltage was greatly reduced, and then, the performance of environmental parameters and process deviations on sub-threshold circuit become critical. The changes in environmental parameters and process deviations easily make traditional 6T SRAM circuit lead to fatal errors, particularly, the Read Static Noise Margin (RSNM) is deteriorated obviously. In order to improve the performance of RSNM, we proposed a novel 8T SRAM bit-cell which uses the read and write separation structure and Partial Dynamic Threshold voltage (PDT) technology. This paper firstly introduces the PDT technology and read and write separation structure; then proposes the novel 8T structure and explains the operating principle of the 8T bit-cell; finally gives the result of the simulation for the stability performance of the 8T bit-cell compare to other 3 kinds of 6T bit-cell. The comparison results show that the proposed 8T bit-cell greatly improves the RSNM of the SRAM bit-cell.

Performance Improvement of GFCAL Circuits

this paper authors have presented a new approach to improve the performance of the glitch free cascadable adiabatic logic (GFCAL) circuit by replacing the triangular power supply with sinusoidal and trapezoidal power supplies (that control the charging and discharging of the capacitive load) and by sizing of transistors. A simulative investigation and performance analysis of proposed approach based 3 bit GFCAL counter, GFCAL JK flip flop and GFCAL 6T-SRAM circuit have also been done. The triangular power supply produces very large delay at the outputs of GFCAL circuits thus it will be very difficult to cascade larger circuits. A solution to provide cascadability is optimization of the delay. In the proposed approach the delay of GFCAL counter for triangular supply has been improved about 40% and 60% whereas for JK flip flop it is 46% and 49% and for 6T SRAM it is 17% and 91% with sinusoidal and trapezoidal power clocks respectively. Keywordscircuit, MOS-Diode, Switching activity.