Circuit performance analysis of graded doping of channel of DGMOS with high‐k gate stack for analogue and digital application

Abstract

Double-gate MOSFET with graded channel doping is studied in this work, where the source and drain ends of the channel are doped with different concentrations to yield two different versions of the above device namely high-low (HL) and low-high (LH). The digital and analogue performances of these devices are investigated, respectively, by implementing 6T SRAM circuit and differential amplifier using the proposed device. Along with the doping variation, a high-K gate stack is also considered for only N type device to observe the effects of the proposed device on its circuit performance. The effective oxide thickness ( EOT ) of p type device is kept constant at 1.5 nm for all the circuit analysis. Hafnium oxide (HfO2) is used as high-K oxide along with silicon-di-oxide (SiO2) to maintain the required EOT of the device. Performance study shows that HL devices are best suited for digital application, whereas its counterpart LH devices perform better in analogue domain.