A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO/sub 2//high-K gate stacks

Abstract

A program with ability to extract device and material parameters of MOS capacitors with nanometer scale effective oxide thicknesses (EOTs) SiO/sub 2//high-K gate dielectrics from experimental gate capacitance (C-V) and gate leakage current (I-V) with high accuracy in a few minutes is demonstrated. Simulated annealing algorithm was used as the optimisation approach. The device parameters such as EOTs, surface substrate doping, flatband voltage and polysilicon doping (if applicable) can be extracted from C-V data, and potentially band offsets, dielectric constants and tunneling masses can be extracted from I-V data of single or multiplayer gate stacks.